• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.6
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• pp.136-150
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• 2010

Due to the effect of indoor coverage problem, the QoS of the indoor users will be degraded dramatically, with the number of indoor users. The femto cell is a popular solution for such problems. Since the price of the femto base station is usually cheap enough, one can sets up huge number of base stations in a small indoor area to reduce the size of communication cell. In this way, the QoS of the indoor users can be improved significantly. Moreover, the data rate can also be increased. However, how to decide an ideal transmitting power according to the surrounding radio environment is not a trivial problem, that still has not been addressed well. If the transmit power of femto base station is too large, the interference to the macro users will be increased. Conversely, if the transmit power of femto base station is too small; the coverage of femto base station will be reduced. To address this problem, we propose a power configuration method in femto base station using Genetic Algorithm by investigating a new fitness function. Furthermore, we adopt the weighted sum approach to improve the user performance in different modes. The simulation results show that the proposed power configuration method can not only improves the downlink SINR, but also enhance the channel capacity for both the Macro cell systems and Femto cell systems compared with some conventional methods.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.23-35
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• 2011

The pedestrian green time is usually long at wide width intersections. This sometimes causes the increase of delay on the whole intersection because of long cycle length and thus small g/C ratio on some direction. In this paper, to improve these problems, staggered pedestrian crossing was evaluated on the vehicular and pedestrian aspects. The results were gained by using both TRANSYT-7F and VISSIM model. The vehicle control delay of the staggered pedestrian crossing was estimated to be decreasing than that of the general pedestrian crossing by 14.9% to 85.6%. The pedestrian average delay of two pedestrian crossing systems was examined by analytical method and VISSIM. According to the analytical method there was no significant difference between each pedestrian crossing system. The pedestrian delay of staggered pedestrian crossing was from 13.4% to 22.3% than the general pedestrian crossing by VISSIM. In conclusion, the staggered pedestrian crossing was more effective than general pedestrian crossing for both the vehicle and the pedestrian. However this conclusion was resulted from micro simulation where traffic volume condition, v/c, was from 0.8 to 1.1.

• Journal of the Korean Data and Information Science Society
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• v.28 no.6
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• pp.1229-1244
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• 2017

In recent years, as demand for data-based analytical methodologies increases in various fields, optimization methods have been developed to handle them. In particular, various constraints required for problems in statistics and machine learning can be solved by convex optimization. Alternating direction method of multipliers (ADMM) can effectively deal with linear constraints, and it can be effectively used as a parallel optimization algorithm. ADMM is an approximation algorithm that solves complex original problems by dividing and combining the partial problems that are easier to optimize than original problems. It is useful for optimizing non-smooth or composite objective functions. It is widely used in statistical and machine learning because it can systematically construct algorithms based on dual theory and proximal operator. In this paper, we will examine applications of ADMM algorithm in various fields related to statistics, and focus on two major points: (1) splitting strategy of objective function, and (2) role of the proximal operator in explaining the Lagrangian method and its dual problem. In this case, we introduce methodologies that utilize regularization. Simulation results are presented to demonstrate effectiveness of the lasso.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.78-86
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• 1999

In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.24-35
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• 2012

In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.

• 전자공학회논문지 IE
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• v.49 no.1
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• pp.18-23
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• 2012

In this paper, a potable device application for DC-DC converter was designed for voltage protection circuit. Voltage protection circuit to offer the under voltage lock out and over voltage protection consists of a comparator and bais circuits were implemented using. XFAB 1um CMOS process, SPICE simulations was confirmed through the characteristics. Simulation results, under voltage lock out input voltage is 4.8 V higher when the turn-on and, 4.2 V less when turn-off. When the input voltage is low voltage is applied can be used to prevent malfunction of the circuit. Over voltage protection is 3.8 V reference voltage when the output voltage caused by blocking circuit prevents device destruction can be used to improve the stability and reliability. The virtual control circuits of the DC-DC converter connected. According to the results of the abnormal voltage, voltage protection circuit behavior was confirmed. The proposed voltage protection circuit of the DC-DC converter cell is useful are considered.

• Journal of IKEEE
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• v.14 no.1
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• pp.25-32
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• 2010

In this paper, we analyze the location accuracy of real-time locating systems (RTLS) in multipath environments, where the RTLS complies with an ISO/IEC 24730-2 international standard. RTLS readers should have an ability not only to recover the transmitted signal but also provide arrival timing information from the received signal. In the multipath environments, in general, the transmitted signal goes through both direct and indirect paths, and then it becomes some distorted form of the transmitted signal. Such multipath components have a critical effect on deciding the first arrival timing of the received signal. To analyze the location error of the RTLS in the multipath environments, we assume two multipath components without considering an additive white Gaussian noise. Through the simulation and real test results, we confirm that the location error does not occur when the time difference between two paths is more than 1.125Tc, but the location error of about 2.4m happens in case of less than 0.5Tc. In particular, we see that the resolvability of two different paths depends largely on the phase difference for the time difference of less than 1Tc.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1172-1182
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• 2014

In these days, many kinds of goods are more light and more integrated. As frequency range of mobile applications have increased to improve performance of antenna furthermore, EMI(ElectroMagnetic Interference) problem has frequently caused by disturbance of antenna in device which aggravates other circuit. This paper proposes a technique for the prediction of noise power to the transmission line from antenna located near the line. Although noise power transferred to transmission line is varied by source impedance of antenna and load impedance of transmission line basically, the power magnitude can be presented in a square form of S-parameter between antenna and transmission line due to small variation of transferred power. For this reason, we can use the index expressed the transferred power varied along geometrical shapes of transmission line. As a result, big difference is occurred along location of antenna especially the bended line. And this such experiment is correspond with simulation, these results have meaning physically considering electromagnetic field distribution in near and far field. HFSS of Ansys and CPW with ground is used in this paper.