• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.98-101
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• 2002

This paper reports a parallel architecture in a HMM based speech recognition system for a low-power LSI design. The proposed architecture calculates output probability of continuous HMM (CHMM) by using concurrent and pipeline processing. They enable to reduce memory access and have high computing efficiency. The novel point is the efficient use of register arrays that reduce memory access considerably compared with any conventional method. The implemented system can achieve a real time response with lower clock in a middle size vocabulary recognition task (100-1000 words) by using this technique.

• Journal of Communications and Networks
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• 제16권6호
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• pp.620-626
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• 2014

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.

• 한국정보보호학회:학술대회논문집
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• 한국정보보호학회 2006년도 하계학술대회
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• pp.164-168
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• 2006

전력 공격은 암호화 연산 과정 중 발생하는 소비 전력의 파형을 측정하여 비밀 정보를 알아내는 공격 방식이다. 이러한 전력 공격에 대한 취약성을 막기 위하여 message blinding, exponent blinding과 같은 기법들이 적용되어 왔다. 본 고에서는 $ECC^{[1]}$암호화 연산 과정에서, r이 임의의 정수일 때, dP=(d-r)P+rP인 관계를 이용하는 exponent blinding기법$^{[2]}$에 대하여 언급하고, 위 기법을 전력 공격의 대응책으로 적용 시 적절히 구현되지 않으면 power attack에 대하여 매우 취약하다는 것을 보인다.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.358-365
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• 2016

We propose a novel application of random forest, a machine learning-based general classification algorithm, to analyze the influence of design attributes on the silicon-to-SPICE (S2S) gap. To improve modeling accuracy, we introduce magnification of learning data as well as randomization for the counting of design attributes to be used for each tree in the forest. From the automatically generated decision trees, we can extract the so-called importance and impact indices, which identify the most significant design attributes determining the S2S gap. We apply the proposed method to actual silicon data, and observe that the identified design attributes show a clear trend in the S2S gap. We finally unveil 10nm key fin-shaped field effect transistor (FinFET) structures that result in a large S2S gap using the measurement data from 10nm test vehicles specialized for model-hardware correlation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1744-1747
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• 2002

In late years, the tendency to shift the design language of electronic circuits from HDL to C-based languages of C/C)1 and so on is strengthened. The current of adopting these software languages thrives by necessity to solve the problem peculiar to HDL that verification of design is difficult. When we use C-based languages, we can describe the design by higher abstraction degree, mount the design as both hardware and software finally and so that express the design part which is not made clear at early stage the same one language. Therefore, the flexibility of design very improves, the design work in environment the range of applying the whole systems become possible. This paper introduces example at having applied C-based languages in image processing LSI design and describes that the design technique of C-based languages is effective for the system design.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.27-33
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• 2010

We have successfully demonstrated a high-pin-count and thin embedded-LSI package to realize next generation's mobile terminals. The following three design key points were applied: (i) Using Cu posts, (ii) Using the coreless structure, (iii) Using a Cu plate as the ground plane. In order to quantitatively determine the contribution of the three points, the five-stage process for reducing the number of metal layers is described by means of the electrical simulation. The point-(i) and (ii) are effective from the viewpoint of the power integrity (PI); that is, these points play important roles in reducing the number of metal layers, and especially the point-(ii) contributes at least twice as the point-(i). The point-(iii) is not effective in the PI, but has a few effects on the signal integrity (SI). For reducing the number of metal layers, we should, at first, pay attention whether the PI characteristics fulfill the specification, and then we should confirm the SI characteristics.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.481-482
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• 2006

Chemical-mechanical polishing, the dominant technology for LSI planarization, is trending to play an important function in micro-electro mechanical systems (MEMS). However, MEMS CMP process has a couple of different characteristics in comparison to LSI device CMP since the feature size of MEMS is bigger than that of LSI devices. Preliminary CMP tests are performed to understand material removal rate (MRR) with blanket wafer under a couple of polishing pressure and velocity. Based on the blanket CMP data, this paper focuses on the consumable approach to enhance MEMS CMP by the adjustment of slurry and pad. As a mechanical tool, newly developed microstructured (MS) pad is applied to compare with conventional pad (IC 1400-k Nitta-Haas), which is fabricated by micro melding method of polyurethane. To understand the CMP characteristics in real time, in-situ friction force monitoring system was used. Finally, the topography change of poly-si MEMS structures is compared according to the pattern density, size and shape as polishing time goes on.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• 정보저장시스템학회논문집
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• 제2권4호
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• pp.224-229
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• 2006

There has been studied flow to minimize the spot size to increase data capacity. Optical data storage devices are being developed near practical limits with wavelength and NA of 405nm and 0.85. There has been studied many types of next generation storage devices such as blu-ray multilayer system, probe based data storage and holographic data storage. Among these data storage devices, solid immersion lens(SIL) based near field recording (NFR) has been widely studied. In this system, SIL is the key component that focuses the laser beam with a very small size which enables ultra high data capacity. Therefore, optical performance evaluation system is required for SIL assembly. In this dissertation, a simple and accurate SIL assembly measurement method is proposed with wedge plate lateral shearing interferometer(LSI). Wedge plate LSI is cheaper than commercialized interferometer, robust to the vibration and the moving distance for phase shifting is large that is order of micrometer. We designed the thickness, wedge angle, material, surface quality and wavelength of wedge plate as 1mm, 0.02degree, fused silica, lamda/10(10-5) and 405nm, respectively. Also, we confirmed simulation and experimental results with quantitative analysis. This simple wedge plate LSI can be applied to different types of SIL such as solid immersion mirror(SIM), hemispherical, super-hemispherical and elliptical SIL.