A Method for Reducing the Number of Metal Layers for Embedded LSI Package |
Ohshima, Daisuke
(System Jisso Research Laboratories, NEC Corporation)
Mori, Kentaro (Device Platforms Research Laboratories, NEC Corporation) Nakashima, Yoshiki (Device Platforms Research Laboratories, NEC Corporation) Kikuchi, Katsumi (Device Platforms Research Laboratories, NEC Corporation) Yamamichi, Shintaro (Device Platforms Research Laboratories, NEC Corporation) |
1 | D. Ohshima, H. Sasaki, K. Mori, Y. Fujimura, K. Kikuchi, Y. Nakashima, T. Funaya, T. Nishiyama, T. Murakami and S. Yamamichi, "Electrical Design and Demonstration of an Embedded High-pin-count LSI Chip Package", Proc. 59th Electronic Components and Technology Conference (ECTC), San Diego, 482, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2009). |
2 | J. Sakai, T. Shimoto, K. Nakase, K. Motonaga, H. Honda and H. Inoue, "Signal Integrity and Power Integrity Properties of FCBGA Based on Ultra-Thin, High-density Package Substrate", Proc. 55th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 284, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2005). |
3 | K. Mori, D. Ohshima, H. Sasaki, Y. Fujimura, K. Kikuchi, Y. Nakashima, T. Funaya, T. Nishiyama, T. Murakami and S. Yamamichi, "A Novel Ultra-thin Package for Embedded High-pin-count LSI Supported by Cu Plate", Proc. 59th Electronic Components and Technology Conference (ECTC), San Diego, 1447, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2009). |