• Journal of Positioning, Navigation, and Timing
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• v.11 no.3
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• pp.173-179
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• 2022

The satellite navigation deception technology disturbs the navigation solution of the receiver by generating a deceptive signal simulating the actual satellite for the satellite navigation receiver mounted on the unmanned aerial vehicle, which is the target of deception. A single spoofing technique that creates a single deceptive position and velocity can be divided into a synchronized spoofing signal that matches the code delay, Doppler frequency, and navigation message with the real satellite and an unsynchronized spoofing signal that does not match. In order to generate a signal synchronized with a satellite signal, a very sophisticated and high precision signal generation technology is required. In addition, the current position and speed of the UAV equipped with the receiver must be accurately detected in real time. Considering the detection accuracy of the current radar technology that detects small UAVs, it is difficult to detect UAVs with an accuracy of less than one chip. In this paper, we assume the asynchrony of a single spoofing signal and propose a region defense technique using multiple spoofing signals.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.33.3-33
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• 2002

Pseudolite (PL) is a kind of signal generator, which transmits GPS-like signal at the ground. However our own made PL is different from a GPS satellite in clock accuracy. GPS satellites are synchronized by use of high precision atomic clocks. But because our PLs use low cost temperature controlled oscillators (TCXO), so it is very difficult to synchronize them. Hence, we should install reference station and use Differential GPS (DGPS) algorithm to calculate user position. By use of this method, we already developed indoor navigation system a few years ago. We named it as 'Asynchronous Pseudolite Indoor Navigation System'. However, this system requires that sampling times of all the receivers...

• Journal of Broadcast Engineering
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• v.1 no.2
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• pp.85-95
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• 1996

The purpose of this paper Is to propose a dubbed signal time-synchroniztion technique based on the SOLA(Synchronized Over-Lap and Add) method which has been widely used to modify the time scale of speech signal. In broadcasting audio recording environments, the high degree of background noise requires dubbing process. Since the time difference between the original and the dubbed signal ranges about 200mili seconds, process is required to make the dubbed signal synchronize to the corresponding image. The proposed method finds he starting point of the dubbing signal using the short-time energy of the two signals. Thereafter, LPC cepstrum analysis and DTW(Dynamic Time Warping) process are applied to synchronize phoneme positions of the two signals. After determining the matched point by the minimum mean square error between orignal and dubbed LPC cepstrums, the SOLA method is applied to the dubbed signal, to maintain the consistency of the corresponding phase. Effectiveness of proposed method is verified by comparing the waveforms and the spectrograms of the original and the time synchronized dubbing signal.

• The KIPS Transactions:PartC
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• v.12C no.1 s.97
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• pp.53-62
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• 2005

The NG-SDH system requires signal synchronization to synchronize incoming ethernet signal with GFP frame. The foreign nation research completes a chipset development until now and it secures a relation technique, but it does not secure a relation technique from domestic. Therefore, in this paper, we presented with signal synchronization method of Ethernet signal through GFP frame. We knew that the synchronized method of Ethernet signal through GFP-F must apply ingress & egress buffer and GFP Idle. We understood that the synchronized method of Ethernet signal through GFP-T must apply GFP Idle and $65B{\_}PAD$, and require maximum 3-bit addition & deletion of idle. Also we showed signal synchronization realization through simulation and obtained MTIE/TDEV characteristics and peak to peak jitter in egress output.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.446-455
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• 2001

In this paper, the precise synchronized clock generator using GPS receiver is presented. The GPS receiver provides a synchronized IPPS signal which guaranties a reliable standard time mark. This signal allows us to do time synchronization and correct the time step. We designed and implemented the precise synchronized clock generator based on DPLL in order to generate a high-resolution clock from a low-cost inaccurate oscillator with ALTERA FLEX EPM6016TC144-3. We also implemented a hardware unit and proved that the unit provides 1MHz clock output which had a high resolution and accuracy when it was combined with GPS receiver.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1582-1590
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• 2019

A new method for reducing the common-mode current generated by the voltage variations in a two-inverter air conditioner system by applying a synchronized pulse-width modulation (PWM) strategy is proposed. The PWM signals of the master-mode inverter are generated based on the reference voltage, while those of the slave-mode inverter are output in the opposite direction when the master-mode inverter changes its switching state. However, the slave-mode control results in a mismatch between the reference voltage and the actual output voltage that is modified by synchronized control operation. The proposed method is capable of reducing and controlling this voltage error by performing signal selection in the vector space of the slave-mode inverter, which mitigates the distortion of the phase current. The efficacy of this method in reducing conducted emissions has been validated both theoretically and experimentally.

• Journal of Satellite, Information and Communications
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• v.10 no.1
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• pp.71-76
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• 2015

In this paper, we developed the hardware GPS signal generator for generating a satellite navigation signal synchronized with Live GPS signal signals and analyzed the performance of signal genterator thorough the experiment For a hardware implementation of the GPS navigation signal synchronous generator, the GPS module may receive a GPS signal in order to generate the same signal as the operation that is transmitted from the current GPS satellite and the synchronized time information and the GPS satellites using the Novatel Inc. OEMStar.In. For generating the GPS synchronization signal, the GPS navigation signal generator was adjusted to a reference clock using the GPS clock synchronous information provided by the GPS receiving module and GPS signals also generated in consideration of the delay of the internal hardware of the generator. In this paper, we analyzed the effect of the receiver via the signal switching between Live GPS signal and generates a signal to measure the performance of the GPS navigation synchronization signal generator. It was confirmed that by the seamless operation of the signal even the moment that the switching of the generated signal from Live GPS signal has occurred through experimentation.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1301-1308
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• 2012

In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

• Journal of IKEEE
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• v.24 no.1
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• pp.178-185
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• 2020

This paper proposes precise time synchronization-based synchronized sampling structure applied HW/SW platform for LAN-based protection of future digital substations. The integrated software of the proposed platform includes IEC 61850 protocol, IEEE 1588 precision time protocol and synchronized sampling structure. The proposed platform expected to provide a basis of an application of future distributed sensing data-based protection and control methods by providing synchronized measurement among IEDs. The implementation of the proposed HW/SW platform technique was performed using TMDXIDK572 multi-core/multi-processor evaluation module and its time synchronization performance and synchronized sampling function were confirmed through the performance tests.