• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1261-1268
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• 2013

This study proposes a voltage and reactive coordinative control strategy with distributed generator (DG) in a distribution power system. The aim is to determine the optimum dispatch schedules for an on-load tap changer (OLTC), distributed generator settings and all shunt capacitor switching on the load and DG generation profile in a day. The proposed method minimizes the real power losses and improves the voltage profile using squared deviations of bus voltages. The results indicate that the proposed method reduces the real losses and voltage fluctuations and improve receiving power factor. This paper proposes coordinated voltage and reactive power control methods that adjust optimal control values of capacitor banks, OLTC, and the AVR of DGs by using a voltage sensitivity factor (VSF) and dynamic programming (DP) with branch-and-bound (B&B) method. To avoid the computational burden, we try to limit the possible states to 24 stages by using a flexible searching space at each stage. Finally, we will show the effectiveness of the proposed method by using operational cost of real power losses and voltage deviation factor as evaluation index for a whole day in a power system with distributed generators.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.1-8
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• 2010

This paper presents the self-oscillating flyback converter for reducing standby power without a control-IC. The proposed self-oscillating flyback converter includes a DC-Blocking capacitor for reducing constant power loss of initial switching path of a conventional self-oscillating flyback converter. it's possible to reduce the standby power to 1W and power efficiency. To confirm the validity of proposed system, comparison of conventional system, verification of experimental results is presented by realization of 35W power system.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.3
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• pp.25-33
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• 1999

In this paper, the method of reducing hanmnics and correcting of power factor in single PWM converter associated with diode rectifier and boost converter is studied. In the general diode rectifier there are sorre problems that discontinuous current of reducing power factor and including distortion of hanmnics at the input current affects other sources. To solve the problems of performance degradation due to pulse wavefonn in the input current, the ac-dc converter in which the hanmnic distortion in the input current is reduced using a third-hanmnic-injected PWM is proposed. A lower power loss of switching and easy configuration of circuit are obtained by adopting discontinuous current mode. Simulation and experimental results of ac-dc converter with 5[kHz] switching frequency are presented and correction of power factor and reduction of total hanmnic distortion was established.lished.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.790-802
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• 2017

This paper proposes the modeling and control strategy to track the MPPs of hybrid PV and Wind power systems, using a new dual input boost converter. The dual input power conditioning system with an independent MPPT control scheme is introduced with minimum number of circuit elements in order to reduce the switching loss, size and cost of the system. Since the operating conditions for the PV and Wind power systems are very distinct from each other, an efficient and superior control system is required to track the MPPs of both renewable sources with the use of a simply-structured single-ended single-inductor converter. The design of Power-Conditioning System (PCS) and detail control strategy are presented in this paper. To provide independent tracking of MPPs, a variable duty-cycle control strategy is employed for the wind system and a variable frequency strategy is employed for the PV system. Finally, the proposed dual-input converter for hybrid power conditioning system is implemented and the hardware test results are presented. From the hardware experiment, it is concluded that the proposed system successfully tracks the MPPs of both of the renewable power systems independently.

• Journal of Electrical Engineering and Technology
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• v.11 no.2
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• pp.329-337
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• 2016

With the increasing deployment of distributed generators in the distribution system, a very large search space is required when dynamic programming (DP) is applied for the optimized dispatch schedules of voltage and reactive power controllers such as on-load tap changers, distributed generators, and shunt capacitors. This study proposes a new optimal voltage and reactive power scheduling method based on dynamic programming with a heuristic searching space reduction approach to reduce the computational burden. This algorithm is designed to determine optimum dispatch schedules based on power system day-ahead scheduling, with new control objectives that consider the reduction of active power losses and maintain the receiving power factor. In this work, to reduce the computational burden, an advanced voltage sensitivity index (AVSI) is adopted to reduce the number of load-flow calculations by estimating bus voltages. Moreover, the accumulated switching operation number up to the current stage is applied prior to the load-flow calculation module. The computational burden can be greatly reduced by using dynamic programming. Case studies were conducted using the IEEE 30-bus test systems and the simulation results indicate that the proposed method is more effective in terms of saving electric charges and improving the voltage profile than loss minimization.

• Journal of Power Electronics
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• v.12 no.3
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Journal of Power Electronics
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• v.18 no.1
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• pp.277-288
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• 2018

Wireless inductive power transfer (IPT) technology is used in many applications today. A compact and high-frequency primary side inverter is one of the most important parts of a WPT system. In this study, a modified class EF-type voltage-fed multi-resonant inverter has been proposed for WPT application at a frequency range of 85-100 kHz. Instead of an infinite input choke inductor, a resonant inductor is used to reduce loss and power density. The peak voltage stress across the MOSFET has been reduced to almost 60% from a class-E inverter using a passive clamping circuit. A simple yet effective design procedure has been presented to calculate the various component values of the proposed inverter. The overall system is simulated using MATLAB/SimPowerSystem to verify the theoretical concepts. A 500-W prototype was built and tested to validate the simulated results. The inverter exhibited 90% efficiency at nearly perfect alignment condition, and efficiency reduced gradually with the misalignment of WPT coils. The proposed inverter maintains zero-voltage switching (ZVS) during considerable load changes and possesses all the inherent advantages of class E-type inverters.

• Proceedings of the Korean Nuclear Society Conference
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• 2004.10a
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• pp.657-658
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• 2004

The reactor protection system (RPS) of HANARO is a safety class system. The reactor is tripped by dropping four shut off rods (SOR). The SOR system consists of a SOR, hydraulic pump, hydraulic cylinder, solenoid valves and a power supply unit which has the AC coil contactor as a switching component. The hydraulic pump lifts up the SOR. The SOR drops by loss of the hydraulic pressure in the hydraulic circuit at the occurrence of voltage sags or interruptions. From this experiment, we knew that the magnitude of the voltage sag which impacts on this system is 70V, 500msec. The reactor regulation system (RRS) of HANARO has four CARs which are connected to the driver through a magnetic clutch. The CAR drops by loss of electromagnetic force of the magnetic clutch when the deeper voltage sags to lower than 10V, 500msec.