• Title/Summary/Keyword: switches

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Train interval control and train-centric distributed interlocking algorithm for autonomous train driving control system (열차자율주행제어시스템을 위한 간격제어와 차상중심 분산형 연동 알고리즘)

  • Oh, Sehchan;Kim, Kyunghee;Choi, Hyeonyeong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.11
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    • pp.1-9
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    • 2016
  • Train control systems have changed from wayside electricity-centric to onboard communications-centric. The latest train control system, the CBTC system, has high efficiency for interval control based on two-way radio communications between the onboard and wayside systems. However, since the wayside system is the center of control, the number of input trains to allow a wayside system is limited, and due to the cyclic-path control flows between onboard and wayside systems, headway improvement is limited. In this paper, we propose a train interval-control and train-centric distributed interlocking algorithm for an autonomous train-driving control system. Because an autonomous train-driving control system performs interval and branch control onboard, both tracks and switches are shared resources as well as semaphore elements. The proposed autonomous train-driving control performs train interval control via direct communication between trains or between trains and track-side apparatus, instead of relying on control commands from ground control systems. The proposed interlocking algorithm newly defines the semaphore scheme using a unique key for the shared resource, and a switch that is not accessed at the same time by the interlocking system within each train. The simulated results show the proposed autonomous train-driving control system improves interval control performance, and safe train control is possible with a simplified interlocking algorithm by comparing the proposed train-centric distributed interlocking algorithm and various types of interlock logic performed in existing interlocking systems.

Performance Evaluation of Output Queueing ATM Switch with Finite Buffer Using Stochastic Activity Networks (SAN을 이용한 제한된 버퍼 크기를 갖는 출력큐잉 ATM 스위치 성능평가)

  • Jang, Kyung-Soo;Shin, Ho-Jin;Shin, Dong-Ryeol
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.8
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    • pp.2484-2496
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    • 2000
  • High speed switches have been developing to interconnect a large number of nodes. It is important to analyze the switch performance under various conditions to satisfy the requirements. Queueing analysis, in general, has the intrinsic problem of large state space dimension and complex computation. In fact, The petri net is a graphical and mathematical model. It is suitable for various applications, in particular, manufacturing systems. It can deal with parallelism, concurrence, deadlock avoidance, and asynchronism. Currently it has been applied to the performance of computer networks and protocol verifications. This paper presents a framework for modeling and analyzing ATM switch using stochastic activity networks (SANs). In this paper, we provide the ATM switch model using SANs to extend easily and an approximate analysis method to apply A TM switch models, which significantly reduce the complexity of the model solution. Cell arrival process in output-buffered Queueing A TM switch with finite buffer is modeled as Markov Modulated Poisson Process (MMPP), which is able to accurately represent real traffic and capture the characteristics of bursty traffic. We analyze the performance of the switch in terms of cell-loss ratio (CLR), mean Queue length and mean delay time. We show that the SAN model is very useful in A TM switch model in that the gates have the capability of implementing of scheduling algorithm.

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Experimental Study on Adfreeze Bond Strength Between Frozen Sand and Aluminium with Varying Freezing Temperature and Vertical Confining Pressure (동결온도와 수직구속응력 변화에 따른 모래와 알루미늄 재료의 접촉면에서 작용하는 동착강도 실험 연구)

  • Ko, Sung-Gyu;Choi, Chang-Ho
    • Journal of the Korean Geotechnical Society
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    • v.27 no.9
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    • pp.67-76
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    • 2011
  • Bearing capacity of pile foundations in cold region is dominated by adfreeze bond strength between surrounding soil and pile perimeter. Adfreeze bond strength is considered to be the most important design parameter for foundations in cold region. Many studies in last 50 years have been conducted to analyze characteristics of adfreeze bond strength. However, most studies have been performed under constant temperature and normal stress conditions in order to analyze affecting factors like soil type, pile material, loading speed, etc. In this study, both freezing temperature and normal stress acting on pile surface were considered to be primary factors affecting adfreeze bond strength, while other factors such as soil type, pile material and loading speed were predefined. Direct shear box was used to measure adfreeze bond strength between Joomoonjin sand and aluminium because it is easy to work for various roughness. Test was performed with temperatures of > $0^{\circ}C$, $-1^{\circ}C$, $-2^{\circ}C$, $-5^{\circ}C$, and $-10^{\circ}C$ and vertical confining pressures of 1atm, 2atm, and 3atm. Based on the test results, the effects of temperature and vertical stress on adfreeze bond strength were analyzed. The test results showed that adfreeze bond strength increases with decreased temperature and increased vertical stress. It was also noted that two types of distinct sections exist, owing to the rate of increase of adfreeze bond strength along the change of freezing temperature: 1)rapidly increasing section and 2)gradually decreasing section. In addition, the results showed that a main factor affecting adfreeze bond strength switches from friction angle to adhesion as freezing temperature decreases.

A 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS Pipeline ADC with Various Circuit Sharing Schemes (다양한 회로 공유기법을 사용하는 10비트 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS Pipeline ADC)

  • Yoon, Kun-Yong;Lee, Se-Won;Choi, Min-Ho;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.53-63
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    • 2009
  • This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

Design of a 2.5V 300MHz 80dB CMOS VGA Using a New Variable Degeneration Resistor (새로운 가변 Degeneration 저항을 사용한 2.5V 300MHz 80dB CMOS VGA 설계)

  • 권덕기;문요섭;김거성;박종태;유종근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.673-684
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    • 2003
  • A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

Development of an Automatic Sprayer Arm Control System for Unmanned Pest Control of Pear Trees (배나무 무인 방제를 위한 약대 자동 제어시스템 개발)

  • Hwa, Ji-Ho;Lee, Bong-Ki;Lee, Min-Young;Choi, Dong-Sung;Hong, Jun-Taek;Lee, Dae-Weon
    • Journal of Bio-Environment Control
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    • v.23 no.1
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    • pp.26-30
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    • 2014
  • Purpose of this study was a development of a sprayer arm auto control system that could be operated according to distance from pear trees for automation of pest control. Auto control system included two parts, hardware and software. First, controller was made with an MCU and relay switches. Two types of ultra-sonic sensors were installed to measure distance from pear trees: one on/off type that detect up to 3 m, and the other continuous type providing 0~5 V output corresponding to distance of 0~3 m. Second, an auto control algorithm was developed to control. Each spraying arm was controlled according to the sensor-based distance from the pear trees. And it could dodge obstacles to protect itself. Max and min signal values were eliminated, when five sensor signals was collected, and then signals were averaged to reduce sensor's noises. According to results of field experiment, auto control test result was better than non auto control test result. Spraying rates were 69.25% (left line) and 98.09% (right line) under non auto control mode, because pear trees were not planted uniformly. But, auto control test's results were 92.66% (left line) and 94.64% (right line). Spraying rate was increased by maintaining distance from tree.

Structural and Functional Analysis of Nitrogenase Fe Protein with MgADP bound and Amino Acid Substitutions (MgADP 결합 및 아미노산 치환 Nitrogenase Fe 단백질의 구조 및 기능 분석)

  • Jeong, Mi-Suk;Jang, Se-Bok
    • Journal of Life Science
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    • v.14 no.5
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    • pp.752-760
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    • 2004
  • The function of the [4Fe-4S] cluster containing iron (Fe-) protein in nitrogenase catalysis is to serve as the nucleotide-dependent electron donor to the MoFe protein which contains the sites for substrate binding and reduction. The ability of the Fe protein to function in this manner is dependent on its ability to adopt the appropriate conformation for productive interaction with the MoFe protein and on its ability to change redox potentials to provide the driving force required for electron transfer. The MgADP-bound (or off) conformational state of the nitrogenase Fe protein structure described reveals mechanisms for long-range communication from the nucleotide-binding sites to control affinity of association with the MoFe protein component. Two pathways, termed switches I and II, appear to be integral to this nucleotide signal transduction mechanism. In addition, the structure of the MgADP bound Fe protein provides the basis for the changes in the biophysical properties of the [4Fe-4S] observed when Fe protein binds nucleotides. The structures of the nitrogenase Fe protein with defined amino acid substitutions in the nucleotide dependent signal transduction pathways of the Switch I and Switch II have been determined by X-ray diffraction methods. These two pathways have been also implicated by site directed mutagenesis studies, structural analysis and analogies to other proteins that utilize similar nucleotide dependent signal transduction pathways. We have examined the validity of the assignment of these pathways in linking the signals generated by MgATP binding and hydrolysis to macromolecular complex formation and intermolecular electron transfer. The results provide a structural basis for the observed biophysical and biochemical properties of the Fe protein variants and interactions within the nitrogenase Fe protein-MoFe protein complex.

Behavioral motivation-based Action Selection Mechanism with Bayesian Affordance Models (베이지안 행동유발성 모델을 이용한 행동동기 기반 행동 선택 메커니즘)

  • Lee, Sang-Hyoung;Suh, Il-Hong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.4
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    • pp.7-16
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    • 2009
  • A robot must be able to generate various skills to achieve given tasks intelligently and reasonably. The robot must first learn affordances to generate the skills. An affordance is defined as qualities of objects or environments that induce actions. Affordances can be usefully used to generate skills. Most tasks require sequential and goal-oriented behaviors. However, it is usually difficult to accomplish such tasks with affordances alone. To accomplish such tasks, a skill is constructed with an affordance and a soft behavioral motivation switch for reflecting goal-oriented elements. A skill calculates a behavioral motivation as a combination of both presently perceived information and goal-oriented elements. Here, a behavioral motivation is the internal condition that activates a goal-oriented behavior. In addition, a robot must be able to execute sequential behaviors. We construct skill networks by using generated skills that make action selection feasible to accomplish a task. A robot can select sequential and a goal-oriented behaviors using the skill network. For this, we will first propose a method for modeling and learning Bayesian networks that are used to generate affordances. To select sequential and goal-oriented behaviors, we construct skills using affordances and soft behavioral motivation switches. We also propose a method to generate the skill networks using the skills to execute given tasks. Finally, we will propose action-selection-mechanism to select sequential and goal-oriented behaviors using the skill network. To demonstrate the validity of our proposed methods, "Searching-for-a-target-object", "Approaching-a-target-object", "Sniffing-a-target-object", and "Kicking-a-target-object" affordances have been learned with GENIBO (pet robot) based on the human teaching method. Some experiments have also been performed with GENIBO using the skills and the skill networks.

Design of a Hybrid Fuzzy Controller for Speed Control of a Hydraulic Elevator Controlled by Inverters (유압식 인버터 엘리베이터의 속도제어를 위한 하이브리드 퍼지제어기의 설계)

  • Han, Gueon-Sang;Kim, Byoung-Hwa;Ahn, Hyun-Sik;Kim, Do-Hyun
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.38 no.1
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    • pp.1-13
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    • 2001
  • Due to the friction characteristics of cylinders and the rail of a passenger car, in the elevator actuated with hydraulic systems, there exist dead zones, which can not be controlled by a PID controller. To overcome the drawbacks, in this paper, we first try a hybrid controller which switches between a fuzzy logic controller and a PID controller. However, because the hybrid control scheme uses only a single type controller, except the switched layer, the high control performance can not be achieved. To solve this problem, we propose a new type fuzzy hybrid control scheme, which outputs of the output mixer arc controlled by a fuzzy logic. The hydraulic elevator system controlled by inverters has more then one switched layers due to the highly nonlinear characteristics. The proposed fuzzy hybrid control scheme achieves improved control performances by using both controllers with weighted outputs depend on the system status, to achieve improved control performances. The effectiveness of the proposed control scheme arc shown by simulation results, which the proposed fuzzy hybrid control method yields good control performance not only in the zero crossing speed region but also in the overall control region including steady-state region.

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A New Variable Degeneration Resistor for Digitally Programmable CMOS VGA (디지털 방식의 이득조절 기능을 갖는 CMOS VGA를 위한 새로운 가변 축퇴 저항)

  • Kwon, Duck-Ki;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.7 no.1 s.12
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    • pp.43-55
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    • 2003
  • A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

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