• Korean Journal of Optics and Photonics
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• v.17 no.1
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• pp.7-17
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• 2006

In this paper, we proposed an optical true time-delay (TTD) for planar phased array antennas (PAAs), which is composed of a wavelength-dependent optical true time delay (WDOTTD) followed by a wavelength-independent optical true time delay (WIOTTD). The WDOTTD is a fiber Bragg gratings (FBGs) Prism and the WDOTTD is a fiber delay-lines matrix of which each component consists of a certain length of fiber connected to cross-ports of a 2${\times}$2 MEMS switch. A 10-GHz 2-bit${\times}$4-bit two-dimensional optical TTD has been fabricated by cascading a WDOTTD with a maximum time delay of 810 ps to a WIOTTD of $\pm$50 ps. Time delay and insertion loss for each radiation angle have been measured. Time delay error for the WIOTTD has been measured to be less than $\pm$1 ps. We have also designed a two-dimensional 10-GHz PAA composed of 8${\times}$8 microstrip patch antenna elements driven by the proposed TTD. The radiation patterns of this PAA have been obtained by simulation and analyzed.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.3
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• pp.96-106
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• 2009

Extending the scale of the distributed processing in a single Ethernet cluster is physically restricted by maximum ports per switch. This paper presents an implementation of MPI-based multicluster consisting of multiple Ethernet switches for extending the scale of distributed processing, and a asymptotical analysis for communication overhead through execution-time analysis model. To determine an optimum task partitioning, we analyzed the processing time for various partitioning schemes, and AAP(accumulator array partitioning) scheme was finally chosen to minimize the overall communication overhead. The scope of data partitioned in AAP was modified to fit for incremented nodes, and suitable load balancing algorithm was implemented. We tried to alleviate the communication overhead through exploiting the pipelined broadcast and flat-tree based result gathering, and overlapping of the communication and the computation time. We used the linear pipeline broadcast to reduce the communication overhead in intercluster which is interconnected by a single link. Experimental results shows nearly linear speedup by the proposed parallel distributed GHT implemented on MPI-based Ethernet multicluster with four 100Mbps Ethernet switches and up to 128 nodes of Pentium PC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.5
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• pp.343-354
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• 2020

Bi-stable mechanism is a system that has two different stable equilibrium positions within its range of motion. It has an ability to stay in two different positions without external power input and despite small disturbances. One of the most bi-stable applied mechanism is a morphing system, such as deployable structures, switch systems, and robot grippers. However, due to the complexity of mechanism and limitation of structure configuration, it is difficult to apply on a morphing system with rotating link mechanism. In this paper, an implementation method of rotational bi-stable mechanism using cylindrical permanent magnets is proposed. The magnetic field and the magnetic force were calculated from electromagnet model of the cylindrical permanent magnet. Based on the model, the force relation between two links containing the cylindrical permanent magnets was estimated. An array of cylindrical permanent magnets was selected for symmetric bi-stability, and an experiment on the link structure with the proposed bi-stable mechanism was performed to investigate the stability against a external torque.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.110-118
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• 2008

The regulated peak power tracking (RPPT) systems such as the series structure and the parallel structure are commonly used in the satellite space power system. However, this structure processes the solar array power to the load through two regulators during one orbit cycle, which reduces the energy transfer efficiency. The series-parallel structure for the RPPT system can improve the power conversion efficiency, but an additional regulator increases the cost, size and weight of the system. In this paper, a simplified series-parallel space power system that consists of two regulators is proposed. The proposed system has the similar energy transfer efficiency with the series-parallel structure by adding one switch to the series structure, which reduces the cost, size and the weight. The large signal stability analyses is provided to understand the four main modes of system operation. In order to compare the energy efficiency with a series structure, the simulation is performed. The experimental verifications are performed using a prototype hardware with TMS320F2812 DSP and 200W solar arrays.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.3
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• pp.485-490
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• 2012

In this paper, driver circuit of LED lights for ships is designed and implemented to replace conventional lights with filament which have short life time due to vibration of ships. The driver of LED module is switching circuit without transformer to reduce volume and cost. As switch circuit controls input 220 VAC with PWM, LED module is reliably driven. Power factor is improved by using valley-fill PFC compensation circuit which is handled to pulse current of switching circuit. Serial-parallel LED circuit is applied to reduce change period of lights of long-term navigation ships. Array of serial-parallel can operate even if some of LEDs is damaged. It is suitable for ships that power consumption and power factor of lights including developed drive circuit have 39Watt and 0.925 respectively.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.11-19
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• 2004

A software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software, is usually used for LEO satellites. This paper proposes a new power-stage circuit that can be available for modularization of a power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We construct a parallel-module converter which is composed of the proposed power-stage and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.26-33
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• 2010

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1535-1544
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• 2017

Advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. FPGA based HIL (Hardware-In-the-Loop) simulators have revolutionized control hardware and software development for power electronics. Common time step sizes in the order of 100ns are sufficient for simulating switching frequency current and voltage ripples. In order to keep the time step as small as possible, ideal switching function models are often used to simulate the phase legs. This often produces inferior results when simulating the discontinuous conduction mode (DCM) and disabled operational states. Therefore, the corresponding measurement and protection units cannot be tested properly. This paper describes a new solution for this problem utilizing a discrete-time PI controller. The PI controller simulates the proper DC and low frequency AC components of the phase leg voltage during disabled operation. It also retains the advantage of fast real-time execution of switch-based models when an accurate simulation of high frequency junction capacitor oscillations is not necessary.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.573-582
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• 2010

In this paper, X-band transceiver for high resolution wideband SAR systems is designed and fabricated. Also as a technique for enhancing the performance, error compensation algorithm is presented. The transceiver for SAR system is composed of transmitter, receiver, switch matrix and frequency generator. The receiver especially has 2 channel mono-pulse structure for ground moving target indication. The transceiver is able to provide the deramping signal for high resolution mode and select the receive bandwidth for receiving according to the operation mode. The transceiver had over 300 MHz bandwidth in X-band and 13.3 dBm output power which is appropriate to drive the T/R module. The receiver gain and noise figure was 39 dB and 3.96 dB respectively. The receive dynamic range was 30 dB and amplitude imbalance and phase imbalance of I/Q channel was ${\pm}$0.38 dBm and ${\pm}$3.47 degree respectively. The transceiver meets the required electrical performances through the individual tests. This paper shows the pulse error term depending on SAR performance was analyzed and range IRF was enhanced by applying the compensation technique.