• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.284-284
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• 2011

Ion sensitive field effect transistor (ISFET)는 용액 중의 각종 이온 농도를 측정하는 반도체 이온 센서이다. ISFET는 작은 소자 크기, 견고한 구조, 즉각적인 반응속도, 기존의 CMOS공정과 호환이 가능하다는 장점이 있다. ISFET의 기본 구조는 기존의 metal oxide semiconductor field effect transistor (MOSFET)에서 고안되었으며, ISFET는 기존의 MOSFET의 게이트 전극 부분이 기준전극과 전해질로 대체되어진 구조를 가지고 있다. ISFET소자의 pH 감지 메커니즘은 감지막의 표면에서 pH용액의 수소이온이 막의 표면에 속박되어 표면전위의 변화를 유발하는 것에 기인한다. 그 결과, 수소이온의 농도에 따라 ISFET의 문턱전압의 변화를 일으키게 되고 드레인 전류의 양 또한 달라지게 된다. 한편, ISFET의 좋은 pH감지특성과 높은 출력특성을 얻기 위하여 high-k물질들이 감지막으로써 지속적으로 연구되어져 왔다. 그 중 Al2O3와 HfO2는 높은 유전상수와 좋은 pH 감지능력으로 인하여 많은 연구가 이루어져온 물질이다. 하지만 HfO2는 높은 유전상수를 갖음에도 불구하고 화학용액에 대한 non-ideal 효과에 취약하다는 보고가 있다. 반면에 Al2O3의 유전상수는 HfO2보다 작지만 화학용액으로 인한 손상에 대하여 강한 immunity가 있는 재료이다. 본 연구에서는, 이러한 각각의 high-k 물질들의 단점을 보안하기 위하여 SiO2/HfO2/Al2O3(OHA) 적층막을 이용한 ISFET pH 센서를 제작하였으며 SOI 기판에서 구현되었다. SOI기판에서 OHA 적층막을 이용한 ISFET 제작이 이루어짐에 따라서 소자의 signal to noise 비율을 증대 시킬것으로 기대된다. 실제로 SOI-ISFET와 같이 제작된 SOI-MOSFET는 1.8${\times}$1010의 높은 on/off 전류 비율을을 보였으며 65 mV/dec의 subthreshold swing 값을 갖음으로써, 우수한 전기적 특성을 보이는 ISFET가 제작이 되었음을 확인 하였다. OHA 감지 적층막의 각 층은 양호한 계면상태, 높은 출력특성, 화학용액에 대한non-ideal 효과에 강한 immunity을 위하여 적층되었다. 결론적으로 SOI과 OHA 적층감지막을 이용하여 우수한 pH 감지 특성을 보이는 pH 센서가 제작되었다.

• Korean Journal of Materials Research
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• v.27 no.4
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• pp.216-220
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• 2017

The effect of electron beam (EB) irradiation on the electrical properties of Zn-Sn-O (ZTO) thin films fabricated using a sol-gel process was investigated. As the EB dose increased, the saturation mobility of ZTO thin film transistors (TFTs) was found to slightly decrease, and the subthreshold swing and on/off ratio degenerated. X-ray photoelectron spectroscopy analysis of the O 1s core level showed that the relative area of oxygen vacancies ($V_O$) increased from 10.35 to 12.56 % as the EB dose increased from 0 to $7.5{\times}10^{16}electrons/cm^2$. Also, spectroscopic ellipsometry analysis showed that the optical band gap varied from 3.53 to 3.96 eV with increasing EB dose. From the results of the electrical property and XPS analyses of the ZTO TFTs, it was found that the electrical characteristic of the ZTO thin films changed from semiconductor to conductor with increasing EB dose. It is thought that the electrical property change is due to the formation of defect sites like oxygen vacancies.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.487-487
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• 2013

According to shrinkage of transistor, interface traps have been recognized as a major factor which limits the process development in manufacturing industry. The traps occur through spontaneous generation process, and spread into the forbidden band. There is a large change of current though a few traps are existed at the Si-SiO2 interface. Moreover, the increased temperature largely affects to the leakage current due to the interface trap. For this reason, we made an effort to find out the relationship between temperature and interface trap. The subthreshold swing (SS) was investigated to confirm the correlation. The simulated results show that the sphere of influence of trap is enlarged according to increase in temperature. To investigate the relationship between thermal energy and surface potential, we extracted the average surface potential and thermal energy (kT) according to the temperature. Despite an error rate of 6.5%, change rates of both thermal energy and average surface potential resemble each other in many ways. This allows that SS is affected by the trap within the range of the thermal energy from the surface energy.

• ETRI Journal
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• v.37 no.6
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• pp.1135-1142
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• 2015

Multilayered ZnO-$SnO_2$ heterostructure thin films consisting of ZnO and $SnO_2$ layers are produced by alternating the pulsed laser ablation of ZnO and $SnO_2$ targets, and their structural and field-effect electronic transport properties are investigated as a function of the thickness of the ZnO and $SnO_2$ layers. The performance parameters of amorphous multilayered ZnO-$SnO_2$ heterostructure thin-film transistors (TFTs) are highly dependent on the thickness of the ZnO and $SnO_2$ layers. A highest electron mobility of $43cm^2/V{\cdot}s$, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on-to-off ratio of $10^{10}$ are obtained for the amorphous multilayered ZnO(1.5nm)-$SnO_2$(1.5 nm) heterostructure TFTs, which is adequate for the operation of next-generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnO-$SnO_2$ heterostructure film consisting of ZnO, $SnO_2$, and ZnO-$SnO_2$ interface layers.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.330-332
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• 2009

Highly stable bottom gate thin film transistors(TFTs) with a zinc indium tin oxide(Zn-In-Sn-O:ZITO) channel layer have been fabricated by rf-magnetron co-sputtering using a indium tin oxide(ITO:90/10), a tin oxide and a zinc oxide targets. The ZITO TFT (W/L=$40{\mu}m/20{\mu}m$) has a mobility of 24.6 $cm^2$/V.s, a subthreshold swing of 0.12V/dec., a turn-on voltage of -0.4V and an on/off ratio of >$10^9$. When gate field of $1.8{\times}10^5$ V/cm was applied with source-drain current of $3{\mu}A$ at $60^{\circ}C$, the threshold voltage shift was ~0.18 V after 135 hours. We fabricated AM-OLED driven by highly stable bottom gate Zn-In-Sn-O TFT array.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.469-473
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• 2017

We investigated the effect of different thin-film thicknesses (25, 30, and 40 nm) on the electrical performance of solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs). The structural properties of the IZO thin films were investigated by atomic force microscopy (AFM). AFM images revealed that the IZO thin films with thicknesses of 25 and 40 nm exhibit an uneven distribution of grains, which deforms the thin film and degrades the performance of the IZO TFT. Further, the IZO thin film with a thickness of 30 nm exhibits a homogeneous and smooth surface with a low RMS roughness of 1.88 nm. The IZO TFTs with the 30-nm-thick IZO film exhibit excellent results, with a field-effect mobility of $3.0({\pm}0.2)cm^2/Vs$, high Ion/Ioff ratio of $1.1{\times}10^7$, threshold voltage of $0.4({\pm}0.1)V$, and subthreshold swing of $0.7({\pm}0.01)V/dec$. The optimization of oxide semiconductor thickness through analysis of the surface morphologies can thus contribute to the development of oxide TFT manufacturing technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1654-1659
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• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.458-462
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• 2011

Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 $cm^2/Vs$, the threshold voltage (Vth) of 2.1 V, the on/off ratio of $4.95{\times}10^6$, and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are tem porarily trapped in the gate insulator, the semiconductor, or the interface between both layers.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.241.2-241.2
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• 2013

최근, 비정질 산화물 반도체 thin film transistor (TFT)는 수소화된 비정질 실리콘 TFT와 비교하여 높은 이동도와 큰 on/off 전류비, 낮은 구동 전압을 가짐으로써 빠른 속도가 요구되는 차세대 투명 디스플레이의 TFT로 많은 연구가 진행되고 있다. 한편, 기존의 MOSFET 제작 시 우수한 박막을 얻기 위해서는 $500^{\circ}C$ 이상의 높은 열처리 온도가 필수적이며 이는 유리 기판과 플라스틱 기판에 적용하는 것이 적합하지 않고 높은 온도에서 수 시간 동안 열처리를 수행해야 하므로 공정 시간 및 비용이 증가하게 된다는 단점이 있다. 따라서, 본 연구에서는 RF sputter를 이용하여 증착된 비정질 InGaZnO pesudo MOSFET 소자를 제작하였으며, thermal 열처리와 microwave 열처리 방식에 따른 전기적 특성을 비교 및 분석하고 각 열처리 방식의 열처리 온도 및 조건을 최적화하였다. P-type bulk silicon 위에 산화막이 100 nm 형성된 기판에 RF 스퍼터링을 이용하여 InGaZnO 분말을 각각 1:1:2mol% 조성비로 혼합하여 소결한 타겟을 사용하여 70 nm 두께의 InGaZnO를 증착하였다. 연속해서 Photolithography 공정과 BOE(30:1) 습식 식각 과정을 이용해 활성화 영역을 형성하여 소자를 제작하였다. 제작 된 소자는 pseudo MOSFET 구조이며, 프로브 탐침을 증착 된 채널층 표면에 직접 접촉시켜 소스와 드레인 역할을 대체하여 동작시킬 수 있어 전기적 특성을 간단하고 간략화된 공정과정으로 분석할 수 있는 장점이 있다. 열처리 조건으로는 thermal 열처리의 경우, furnace를 이용하여 각각 $300^{\circ}C$, $400^{\circ}C$, $500^{\circ}C$, $600^{\circ}C$에서 30분 동안 N2 가스 분위기에서 열처리를 실시하였고, microwave 열처리는 microwave를 이용하여 각각 400 W, 600 W, 800 W, 1000 W로 20분 동안 실시하였다. 그 결과, furnace를 이용하여 열처리한 소자와 비교하여 microwave 를 통해 열처리한 소자에서 subthreshold swing (SS), threshold voltage (Vth), mobility 등이 개선되는 것을 확인하였다. 따라서, microwave 열처리 공정은 향후 저온 공정을 요구하는 MOSFET 제작 시의 훌륭한 대안으로 사용 될 것으로 기대된다.