• 제목/요약/키워드: sub channel

검색결과 922건 처리시간 0.025초

말초 및 중추신경계에서 칼슘채널 및 NMDA 매개 채널의 억제제로의 진세노사이드 Rg3의 효과 (The Effects of Ginsenoside Rg3 as a Potent Inhibitor of Ca2+ Channels and NMDA-gated Channels in the Peripheral and Central Nervous Systems)

  • 임혜원
    • Journal of Ginseng Research
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    • 제27권3호
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    • pp.120-128
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    • 2003
  • Alternative medicines such as herbal products are increasingly being used for preventive and therapeutic purposes. Ginseng is the best known and most popular herbal medicine used worldwide. In spite of some beneficial effects of ginseng on the nervous system, little scientific evidence shows at the cellular level. In the present study, I have examined the direct modulation of ginseng total saponins and individual ginsenosides on the activation of $Ca^{2+}$ channels and NMDA-gated channels in cultured rat dorsal root ganglion (DRG) and hippocampal neurons, respectively. In DRG neurons, application of ginseng total saponins suppressed high-voltage-activated $Ca^{2+}$ channel currents and ginsenoside Rg$_3$, among the 11 ginsenosides tested, produced the strongest inhibition on $Ca^{2+}$ channel currents. Occlusion experiments using selective $Ca^{2+}$ channel blockers revealed that ginsenoside Rg$_3$ could modulate L-, N-, and P/Q-type currents. In addition, ginsenoside Rg$_3$ also proved to be an active component of ginseng actions on NMDA receptors in cultured hippocampal neurons. Application of ginsenoside Rg$_3$ suppressed NMDA-induced [Ca$^{2+}$]$_{i}$ increase and -gated channels using fura-2-based digital imaging and patch-clamp techniques, respectively. These results suggest that the modulation of $Ca^{2+}$ channels and NMDA receptors by ginsenoside Rg$_3$ could be part of the pharmacological basis of ginseng actions in the peripheral and central nervous systems.ous systems.

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO2 or SiO2 Trench Isolation

  • Nam, Hyohyun;Park, Seulki;Shin, Changhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권4호
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    • pp.427-435
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    • 2014
  • Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of $HfO_2$ (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with $HfO_2$, and the VSTI region is filled with $SiO_2$) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with $HfO_2$, and the STI region is filled with $SiO_2$) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate ($C_{gg}$) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest $C_{gg}$ value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

D2D 통신 시스템을 위한 CAZAC 시퀀스 기반 링크 스케줄링 기법 (Link Scheduling Method Based on CAZAC Sequence for Device-to-Device Communication)

  • 강위필;황원준;최형진
    • 한국통신학회논문지
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    • 제38A권4호
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    • pp.325-336
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    • 2013
  • 대표적인 D2D (Device-to-Device) 통신 시스템 중 하나인 Qualcomm사의 FlashLinQ 시스템에서는 링크 스케줄링 과정을 낮은 복잡도로 실현할 수 있도록 하기 위해 단일-톤 (single-tone) 신호를 이용한 우선순위 및 SIR (Signal-to-Interference power Ratio) 기반의 링크 스케줄링 기법을 수행한다. 하지만 다중 경로 채널 환경에서는 주파수 선택적 페이딩의 영향으로 단일-톤 위치에서와 실제 데이터가 전송되는 전체 대역에서의 수신 전력 간 오차가 발생할 수 있으며, 이는 공평성 측면에서 문제가 될 뿐만 아니라 셀 전체 전송률 상의 손실을 일으킬 수 있다. 따라서, 본 논문에서는 이러한 문제를 해결하기 위해 CAZAC (Constant Amplitude Zero Auto-Correlation) 시퀀스의 상관 특성을 이용해 전체 대역에 대한 SIR 에 가까운 값을 획득할 수 있는 링크 스케줄링 기법을 제안한다. 제안 기법은 전체 대역을 다수의 sub-block 으로 구분하고 각 sub-block 마다 링크의 우선순위에 해당하는 순환 오프셋 (cyclic offset) 을 적용한 CAZAC 시퀀스를 전 대역에 걸쳐 전송하여, 수신 신호와 참조 신호간의 순환 상호 상관 연산 (cyclic cross-correlation)을 통해 전체 대역에 대한 SIR 에 근접한 값을 획득할 수 있다.

CTF-F 구조를 가진 3D NAND Flash Memory에서 Gate Controllability 분석 (The Analysis of Gate Controllability in 3D NAND Flash Memory with CTF-F Structure)

  • 김범수;이종원;강명곤
    • 전기전자학회논문지
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    • 제25권4호
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    • pp.774-777
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    • 2021
  • 본 논문은 Charge Trap Flash using Ferroelectric(CTF-F) 구조를 가진 3D NAND Flash Memory gate controllability에 대해 분석했다. Ferroelectric 물질인 HfO2는 polarization 이외에도 high-k 라는 특징을 가진다. 이러한 특징으로 인해 CTF-F 구조에서 gate controllability가 증가하고 Bit Line(BL)에서 on/off 전류특성이 향상된다. Simulation 결과 CTF-F 구조에서 String Select Line(SSL)과 Ground Select Line(GSL)의 채널길이는 100 nm로 기존 CTF 구조에 비해 33% 감소했지만 거의 동일한 off current 특성을 확인했다. 또한 program operation에서 channel에 inversion layer가 더 강하게 형성되어 BL을 통한 전류가 약 2배 증가한 것을 확인했다.

박막이 부착된 채널내의 2차원 층류유동장에 대한 연구 (Study on Two-Dimensional Laminar Flow through a Finned Channel)

  • 윤석현;정재택
    • 한국전산유체공학회지
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    • 제7권3호
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    • pp.53-59
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    • 2002
  • A two-dimensional laminar flow through a channel with a pair of symmetric vertical fins is investigated. At far up- and down-stream from the fins, the plane Poiseuille flow exists in the channel. The Stokes flow for this channel is first investigated analytically and then the other laminar flows by numerical method. For analytic method, the method of eigen function expansion and collocation method are employed. In numerical solution for laminar flows, finite difference method(FDM) is used to obtain vorticity and stream function. From the results, the streamline patterns are shown and the additional pressure drop due to the attached fins and the force exerted on the fin are calculated. It is clear that the force depends on the length of fins and Reynolds number. When the Reynolds number exceeds a critical value, the flow becomes asymmetric. This critical Reynolds number Re/sub c/ depends on the length of the fins.

DS-CDMA DMB 하향링크에서의 블라인드 신호공간 채널추정 기법 (Blind Signal Subspace Channel Estimation technique for DS-CDMA DMB downlink)

  • 양완철;이병섭
    • 한국통신학회논문지
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    • 제29권9A호
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    • pp.1039-1047
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    • 2004
  • 본 논문에서는 신호공간과 장음공간과의 직교성을 이용하는 종래의 부분공간 방식과는 달리 신호공간만을 이용하여 채널응답을 추정해낼 수 있는 긴 코드 DSCDMA DMB 하향링크 시스템에서의 새로운 채널추정기법을 제안한다. 신호공간만을 이용하므로 제안된 기법은 종래의 부분공간 방식에서의 공분산 행렬 사이즈 문제를 해결할 수 있고 따라서 실제 구현 가능한 적정한 사이즈의 공분산 행렬로 부분공간 분석을 통한 채널추정기업에 사용될 수있다.

Short Channel GaAs MESFET의 채널전하분포와 채널전하에 의한 전위장벽의 변화 (Potential Barrier Shift Caused by Channel Charge in Short Channel GaAs MESFET)

  • 원창섭;이명수;류세환;한득영;안형근
    • 한국전기전자재료학회논문지
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    • 제19권9호
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    • pp.793-799
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    • 2006
  • In this paper, the gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. the gate to drain current has been obtained with ground source. The difference between two currents has been tested and proves that the electric field generated by channel charge effect against the image force lowering.

Analysis of Short Channel Effects Using Analytical Transport Model For Double Gate MOSFET

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • 제5권1호
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    • pp.45-49
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    • 2007
  • The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

근막통증증후군의 통증유발점 치료를 위한 멀티어레이 전극과 프로그램 가능한 다채널 전기자극기 개발 (Development of Multi-Array Electrode and Programmable Multi-channel Electrical Stimulator for Firing Trigger Point of Myofascial Pain Syndrome)

  • 김수홍;김수성;전계록
    • 대한의용생체공학회:의공학회지
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    • 제36권5호
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    • pp.221-227
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    • 2015
  • In this study, Multi-Array Electrodes (MAE) and Programmable Multi-channel Electrical Stimulator (PMES) were implemented for firing Trigger Points (TPs) of the patient with Myofascial Pain Syndrome (MPS). MAE has 25 Ag/AgCl electrodes arranged in the form of array ($5{\times}5$) fabricated with flexible pad, which are applicable to be easy-attached to curved specific region of the human body. PMES consisted of 25 channels. Each channel was to generate various electric stimulus patterns (ESPs) by changing the mono-phasic or bi-phasic of ESP, On/Off duration of ESP, the interval between ESP, and amplitude of ESP. PMES hardware was composed of Host PC, Stimulation Pattern Editing Program (SPEP), and Multi-channel Electrical Stimulator (MES). Experiments were performed using MAE and PMES as the following. First experiment was performed to evaluate the function for each channel of Sub- Micro Controller Unit (SMCU) in MES. Second experiment was conducted on whether ESP applied from each channel of SMCU in PMES was focused to the electrode set to the ground, after applying ESP being output from each channel of SMCU in PMES to MAE.

자기정렬 DMOS 트랜지스터의 채널 길이와 채널 Punchthrough에 관한 고찰 (A Study on the Channel Length and the Channel Punchthrough of Self-Aligned DMOS Transistor)

  • 김종오;김진형;최종수;윤한섭
    • 대한전자공학회논문지
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    • 제25권11호
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    • pp.1286-1293
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    • 1988
  • 자기정렬 DMOS 트랜지스터의 채널 길이에 관한 수식을 2차원적인 Caussian 농도분포식으로부터 유도하였다. 본 논문에서는 제시된 채널 길이에 관한 수식은 기판의 농도, 이중확산된 각 영역의 표면 농도와 수직 접합 깊이의 함수로 이루어져 있으며, 계산된 실험치와 잘 일치하고 있다. 또한 고전압용 DMOS 트랜지스터에서 채널 punchthrough를 억제할 수 있는 최소 채널 길이를 채널영역의 평균농도를 이용하여 계산하였으며 소자 simulation을 통하여 최적의 채널 조건(채널농도분포 및 채널 길이)를 예측할 수 있음을 확인하였다.

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