• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1333-1336
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• 1998

Hydrogenated amorphous silicon(a-Si:H) films which were deposited by plasma enhanced chemical deposition(PECVD) have been recrystallized by the two-step rapid thermal annealing(RTA) employing the halogen lamp. The a-Si:H films evolve hydrogen explosively during the high temperature crystallzation step. In result, the recrystallized polycrystalline silicon(poly-Si) films have poor surface morphology. In order to avoid the hydrogen evolution, the films have undergone the dehydrogenation step prior to the crystallization step Before the RTA process, the active area of thin film transistors (TFT's) was patterned. The prepatterning of the a-Si:H active islands may reduce thermal damage to the glass substrate during the recrystallization. The computer generated simulation shows the heat propagation from the a-Si:H islands into the glass substrate. We have fabricated the poly-Si TFT's on the silicon wafers. The maximun ON/OFF current ratio of the device was over $10^5$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.60-60
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• 2010

1-D nanostructured materials have much more attention because of their outstanding properties and wide applicability in device fabrication. Bismuth oxide($Bi_2O_3$) is an important p-type semiconductor with main crystallographic polymorphs denoted by $\alpha-$, $\beta-$, $\gamma-$, and $\delta-Bi_2O_3$[1]. Due to its unique optical and electrical properties, $Bi_2O_3$ has been extensively investigated for various applications in gas sensors, photovoltaic cells, fuel cells, supercapacitors[2-4]. In this study, $Bi_2O_3$ NWs were grown by two step annealing process: in the first step, after annealing at $270^{\circ}C$ for 10h in a vaccum($3{\times}10^{-6}$ torr), we can obtain the bismuth nanowires. In the second step, after annealing at $300^{\circ}C$ for 2h in $O_2$ ambient, we successfully fabicated $Bi_2O_3$nanowires.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.464-469
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• 1999

Recently, the need for designing multi-stage gear drive has been increased as the hear drives are used more in the applications with high-speed and small volume. The design of multi-stage gear drives includes not only dimensional design but also configuration design of various machine elements. Until now, however, the researches on the design of gear drives are mainly focused on the single-stage gear drives and the design practices for multi-stage gear drives, especially in configuration design activity, mainly depend on the experiences and 'sense' of the designer by trial and error. We propose a design algorithm to automate the dimension design and the configuration design of multi-stage gear drives. The design process consists of four steps. The number of stage should be determined in the first step. In second step, the gear ratios of each reduction stage are determined using random search, and the ratios are basic input for the dimension design of gears, which is performed by the exhaustive search in third step. The designs of gears are guaranteed by the pitting resistance and bending strength rating practices by AGMA rating formulas. In configuration design, the positions of gears are determined to minimize the volume of gearbox using simulated annealing algorithm. The effectiveness of the algorithm is assured by the design example of a 4-stage gear drive.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.87-90
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• 1999

We have studied the annealing effects of 570 (SrTiO$_3$) single crystal substrate and the I-V properties of step-edge junctions after Ar ion milling. YBa$_2Cu_3O_7$ (YBCO) thin films are fabricated on the substrates by using pulsed laser deposition (PLD) and photolithography. The surface of Ar ion milled substrate was characterized with atomic force microscope (AFM) and scanning electron microscope (SEM) images. After the substrate was damaged by milling, the critical current density of YBCO thin films deposited on the substrate was lowered. The annealing of the damaged substrate at about 1000 $^{\circ}C$ recovered the critical current density to that before the milling. Futhermore the annealing helped junction formation due to high quality film and increased the yield rate for the fabrication of high quality step-edge junction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.115-117
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• 2005

In this paper, we formed the shallow junction by preamorphization and low energy ion implantation. And a simulator is designed for predicting the annealing process results. Especially, if considered the applicable to single step annealing process(RTA, FA) and dual step annealing process(RTA+FA, FA+RTA). In this simulation, the ion implantation model and the boron diffusion model are used. The Monte Carlo model is used for the ion implantation. Boron diffusion model is based on pair diffusion at nonequilibrium condition. And we considered that the BI-pairs lead the diffusion and the boron activation and clustering reaction. Using the boundary condition and initial condition, the diffusion equation is solved successfully. The simulator is made ofC language and reappear the experimental data successfully.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.2
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• pp.174-179
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• 2011

This paper focuses on the optimal step-over value for magnetic tool path. Since magnetic flux density is changed according to distance from center of magnetic tool. Enhanced surface roughness is also different according to change of radius. Therefore, to get a identical surface roughness on workpiece, it is necessary to find optimal tool path including step-over. In this study, response surface models for surface roughness according to change of radiuses were developed, and then optimal enhanced surface roughness for each radius was selected using genetic algorithm and simulated annealing to investigate relation between radius and surface roughness. As a result, it found that step-over value of 6.6mm is suitable for MAP of magnesium alloy.

• Transactions of Materials Processing
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• v.11 no.7
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• pp.581-588
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• 2002

Among the processes to produce micro lens, the process using press molding is a new technology to simplify the process, but it contains many unknown variables. The press-molding process proposed in this paper was simplified into two step process, the first step is the pressing to design the preform for glass element, the second step is the annealing to reduce the residual stress. It is important to estimate the amount of shrinkage of glass gob and the residual stress during process. It Is difficult to evaluate the process variables as mentioned above through the experiment. The influences due to process variables was evaluated by using FEM parametric analysis. The results in this paper can be applicable to produce micro lens.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• Advances in Energy Research
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• v.3 no.2
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• pp.117-124
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• 2015

In this paper, we have reported an enhancement in thermoelectric properties of un-doped zinc oxide (ZnO) grown by molecular beam epitaxy (MBE) on silicon (001) substrate by annealing treatment. The grown ZnO thin films were annealed in oxygen environment at $500^{\circ}C-800^{\circ}C$, keeping a step of $100^{\circ}C$ for one hour. Room temperature Seekbeck measurements showed that Seebeck coefficient and power factor increased from 222 to $510{\mu}V/K$ and $8.8{\times}10^{-6}$ to $2.6{\times}10^{-4}Wm^{-1}K^{-2}$ as annealing temperature increased from 500 to $800^{\circ}C$ respectively. This observation was related with the improvement of crystal structure of grown films with annealing temperature. X-ray diffraction (XRD) results demonstrated that full width half maximum (FWHM) of ZnO (002) plane decreased and crystalline size increased as the annealing temperature increased. Photoluminescence study revealed that the intensity of band edge emission increased and defect emission decreased as annealing temperature increased because the density of oxygen vacancy related donor defects decreased with annealing temperature. This argument was further justified by the Hall measurements which showed a decreasing trend of carrier concentration with annealing temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.06a
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• pp.86-86
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• 1998