• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.771-780
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• 2016

Detecting a set of longest paths is one of the crucial steps in static timing analysis and optimization. Recently, the process variation during manufacturing affects performance of the circuit design due to nanometer feature size. Measuring the performance of a circuit prior to its fabrication requires a considerable amount of computation time because it requires multi-corner and multi-mode analysis with process variations. An efficient algorithm of detecting the K-most critical paths in multi-corner multi-mode static timing analysis (MCMM STA) is proposed in this paper. The ISCAS'85 benchmark suite using a 32 nm technology is applied to verify the proposed method. The proposed K-most critical paths detection method reduces about 25% of computation time on average.

• 한국정보처리학회논문지
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• 제4권6호
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• pp.1481-1494
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• 1997

실시간 시스템에서 시간적 제약의 불이행의 커다란 손실을 가져오며, 이를 위한 동적 스케쥴링은 유연성을 제공하는 대신 스케쥴링 오버헤드와 분석작업의 복잡성으로 인하여 스케쥴성을 예측하기 어려움이 있다. 반면, 정적 스케쥴링은 수행 중 오버헤드가 없으므로 정확한 시간을 예측할 수 있는 장점이 있다. 따라서 명령어 수준의 정적 스케쥴링과 시간 분석을 통하여 시스템의 시간적 정확도를 보장할 수 있다. 본 논문에서는 확정된 시간 분석을 위하여 befor와 after의 시간 제약을 고급 언어에 표현하고 이를 근거로 시간적 분석에 기반을 둔 컴파일러의 명령어 수준의 스케쥴링 알고리즘을 제안하였다. 이 스케쥴링의 특징은 명령어 수준의 스케쥴링을 위한 도메인이 지나치게 과대하므로 향상된 적합 유전자 알고리즘을 적용한 것이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.357-360
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• 2002

In this paper, we propose a technique to eliminate 1,he effect of false paths in the calculation of the distribution of the maximum delay of a given CMOS combinatorial circuit, when distributions of interconnect delays and gate switching delays of the circuit are given. The technique can be incorporated into our algorithm for the statistical static timing analysis, which can take correlations of the delays into account.

• Journal of Communications and Networks
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• 제6권2호
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• pp.182-191
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• 2004

In this paper, performances of different ultra-wideband (UWB) modulation schemes in the presence of timing jitter are evaluated and compared. Static and Rayleigh fading channels are considered. For fading channels, Oat and dispersive channels are assumed. First, bit error rate (BER) performances for each case are derived for a fixed value of timing jitter. Later, a uniform distribution of jitter is assumed to evaluate the performance of the system, and the theoretical results are verified by computer simulations. Finger estimation error is treated as timing jitter and an appropriate model is generated. Furthermore, a worst case distribution that provides an upper bound on the system performance is presented and compared with other distributions. Effects of timing jitter on systems employing different pulse shapes are analyzed to show the dependency of UWB performance on pulse shape. Although our analysis assumes uniform timing jitter, our framework can be used to evaluate the BER performance for any given probability distribution function of the jitter.

• 한국컴퓨터정보학회논문지
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• 제15권4호
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• pp.37-45
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• 2010

시간적 정확성을 필요로 하는 시스템은 신뢰성을 위하여 실행시간에 관한 정확한 설계와 검증이 필요하다. 따라서 실행시간의 분석을 위한 개발 지원 도구가 필요하고 이를 위한 많은 연구가 진행되고 있다. 이러한 개발 지원 도구의 분석 방법은 정적 분석 방법과 측정 기반 분석 방법의 두 가지로 구분된다. 먼저 정적 분석은 짧은 시간에 분석이 가능하지만, 다양한 하드웨어의 존재로 인해 I/O 정보 예측이 어려워 분석 결과의 신뢰성이 떨어진다. 두 번째로 측정 기반 분석은 실제 결과에 근접한 분석이 가능하지만, 사용하기 어렵고 분석에 걸리는 시간이 길다. 이러한 분석 방법의 문제를 해결하기 위하여 본 논문에서는 정적 분석 과정에 소프트웨어 감시 방안을 적용한 방법을 제안한다. 제안하는 분석 방안은 정적 분석을 통해 감시가 필요한 대상을 자동으로 결정하고 감시 결과를 통해 과대 예측을 줄일 수 있다. 따라서 감시에 대한 어려움과 시간의 부하를 줄이고 정적 분석의 가장 큰 문제점인 신뢰성을 향상시킬 수 있다.

• Journal of Electrical Engineering and information Science
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• 제1권1호
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• pp.118-128
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• 1996

In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Journal of Positioning, Navigation, and Timing
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• 제5권1호
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• pp.21-28
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• 2016

The Wide Area Differential Global Positioning System (WADGPS) that uses a number of Global Navigation Satellite System (GNSS) reference stations are implemented with various types and provide services as it can service a wide range of areas relatively. This paper discusses a constellation design of reference stations and performance analysis of the WADGPS. It presented performance results of static and dynamic users when wide area correction algorithm was applied using eight reference stations.

• Journal of Computing Science and Engineering
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• 제6권4호
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• pp.267-278
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• 2012

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

• ETRI Journal
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• 제38권3호
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.