• 한국진공학회지
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• 제4권S1호
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• pp.138-144
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• 1995

It is commonly believed that high permittivity materials will be necessary for future high density Gbit DRAMs. In a first part, we explain the choice of SrTiO3 by ECR MOCVD for Gbit-scale DRAMs. In a second part, after describing the ECR MOCVD system and presenting the requirements SrTiO3 thin films should meet for use in Gbit-scale DRAMs, the physical and electrical properties of srTiO3 thi film prepared by ECR MOCVD are then studied. A stacked capacitor technology, suitable for use in 1 Gbit DRAM, and comprising high permittivity SrTiO3 thin films prepared by ECR MOCVD at $450^{\circ}C$ on electron beam and RIE patterned RuO2/TiN storage nodes is finally described.

• 센서학회지
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• 제1권2호
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• pp.117-123
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• 1992

적층구조의 Pt-Sn 박막을 히터 위에서 열산화하여 $Pt-SnO_{2-x}$ 박막형 CO 가스감지소자를 제조하였다. 열증착법으로 증착된 Sn의 두께는 $4000{\AA}$이었으며 그 위에 D.C. sputtering법으로 증착된 Pt의 두께는 $14{\AA}{\sim}71{\AA}$ 이었다. XRD 분석에서 $Pt-SnO_{2-x}$ 박막은 $200{\AA}$ 정도의 입경과 주방향성이 (110)인 $(SnO_{2}){\cdot}6T$ 결정상을 보였다. $Pt-SnO_{2-x}$ 박막소자(Pt 두께 : $43{\AA}$)는 6000 ppm의 CO에 대해 80% 정도의 감도와 CO에 대해 높은 선택도를 나타내었다. 그리고 CO에 고감도를 갖는 $Pt-SnO_{2-x}$ 박막소자의 열산화 온도와 동작온도가 각각 $500^{\circ}C$와 $200^{\circ}C$이었다.

• 한국산학기술학회논문지
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• 제21권1호
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• pp.8-13
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• 2020

IC 패키지와 같이 두께가 수백 마이크로미터 정도로 매우 얇은 기판에서 뒤틀림 불량을 일으키는 가장 큰 원인은 응력이다. 일반적으로 응력은 기판 위에 서로 다른 물질을 적층할 때, 결정구조 및 그에 따른 열팽창 계수의 차이로 인해 발생한다. 본 연구에서는 사각형의 박막 패턴이 적층된 기판에 발생하는 응력의 거동을 수치적으로 분석하였다. 먼저 기판 변위를 구하고, 이를 이용하여 기판 변형률과 응력을 구하였다. 박막 패턴의 가장자리에 인장력이 집중된 경우, 박막 패턴의 가장자리를 중심으로 수직 응력과 전단 응력이 발생한다. 수직 응력은 박막 패턴의 가장자리와 꼭짓점 부근에 발생한다. 전단 응력도 박막 패턴의 가장자리를 중심으로 발생하나 수직 응력과는 달리 꼭짓점 부근에는 나타나지 않는다. 또한 가장자리를 중심으로 전단 응력의 크기와 방향이 바뀌는 것을 확인할 수 있었다. 박막패턴 가장자리 힘이 동일할 때, 수직 응력은 전단 응력에 비해 10배 정도의 값을 나타내었다. 이는 뒤틀림 불량을 일으키는 가장 큰 원인이 수직 응력임을 나타낸다.

• Transactions on Electrical and Electronic Materials
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• 제11권2호
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• pp.73-76
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• 2010

The copper indium disulfide ($CuInS_2$) thin film was manufactured using sputtering and thermal evaporation methods, and the annealing with sulfurization process was used in the vacuum chamber to the substrate temperature on the glass substrate, the annealing temperature and the composition ratio, and the characteristics thereof were investigated. The $CuInS_2$ thin film was manufactured by the sulfurization of a soda lime glass (SLG) Cu/In/S stacked [1] elemental layer deposited on a glass substrate by vacuum chamber annealing [2] with sulfurization for various times at a temperature of substrate temperature of $200^{\circ}C$. The structure and electrical properties of the film was measured in order to determine the optimum conditions for the growth of $CuInS_2$ ternary compound semiconductor $CuInS_2$ thin films with a non-stoichiometric composition. The physical properties of the thin film were investigated under various fabrication conditions [3,4], including the substrate temperature, annealing temperature and annealing time by X-ray diffraction (XRD), field Emission scanning electron microscope (FE-SEM), and Hall measurement systems. [5] The sputtering rate depending upon the DC/RF power was controlled so that the composition ratio of Cu versus In might be around 1:1, and the substrate temperature affecting the quality of the film was varied in the range of room temperature (RT) to $300^{\circ}C$ at intervals of $100^{\circ}C$, and the annealing temperature of the thin film was varied RT to $550^{\circ}C$ in intervals of $100^{\circ}C$.

• Current Photovoltaic Research
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• 제7권1호
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• pp.1-8
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• 2019

The $Cu(In,Ga)Se_2$ (CIGS) thin film obtained by two-step process (metal deposition and Se annealing) has a rough surface morphology and many voids at the CIGS/Mo interface. To solve the problem a precursor that contains Se was employer by depositing a (In,Se)/(Cu,Ga) stacked layer. We devised a two-step annealing (vacuum pre-annealing and Se annealing) for the precursor because direct annealing of the precursor in Se environment resulted in the small grains with unwanted demarcation between stacked layers. After vacuum pre-annealing up to $500^{\circ}C$ the CIGS film consisted of CIGS phase and secondary phases including $In_4Se_3$, InSe, and $Cu_9(In,Ga)_4$. The secondary phases were completely converted to CIGS phase by a subsequent Se annealing. A void-free CIGS/Mo interface was obtained by the two-step annealing process. Especially, the CIGS film prepared by vacuum annealing $450^{\circ}C$ and subsequent Se annealing $550^{\circ}C$ showed a densely-packed grains with smooth surface, well-aligned bamboo grains on the top of the film, little voids in the film, and also little voids at the CIGS/Mo interface. The smooth surface enhanced the cell performance due to the increase of shunt resistance.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.653-655
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• 2003

Using stacked organic gate insulators and active layer of pentacene deposited at elevated temperatures, pentacene-based organic thin-film transistors(OTFTs) with improved electrical characteristics have been fabricated. Stacked PVP(Polyvinylphenol)-polystyrene gate insulators could compensate the demerits and take advantage of the merits of each other [1]. Also, for the better device performance, moderate substrate heating and high deposition rate of pentacene active layer was adopted [2, 3].

• Macromolecular Research
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• 제14권1호
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• pp.38-44
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• 2006

Vacuum deposited copper phthalocyanine (CuPc) was placed as a thin interlayer between indium tin oxide (ITO) electrode and a hole transporting layer (HTL) in a multi-layered, organic, light-emitting diode (OLEOs). The well-stacked CuPc layer increased the stability and efficiency of the devices. Thermal annealing after CuPc deposition and magnetic field treatment during CuPc deposition were performed to obtain a stacked-CuPc layer; the former increased the stacking density of the CuPc molecules and the alignment of the CuPc film. Thermal annealing at about 100$^{circ}C$ increased the current flow through the CuPc layer by over 25$\%$. Surface roughness decreased from 4.12 to 3.65 nm and spikes were lowered at the film surface as well. However, magnetic field treatment during deposition was less effective than thermal treatment. Eventually, a higher luminescence at a given voltage was obtained when a thermally-annealed CuPc layer was placed in the present, multi-layered, ITO/CuPc/NPD/Alq3/LiF/AI devices. Thermal annealing at about 100$^{circ}C$ for 3 h produced the most efficient, multi-layered EL devices in the present study.

• 센서학회지
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• 제3권1호
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• pp.78-82
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• 1994

Single-phase $CuInS_{2}$ 박막을 제작하고 열처리에 따른 특성을 분석하였다. 박막제작은 S, In 및 Cu를 차례로 적층시킨 다음 질소분위기에서 열처리를 하여 Chalcopyrite 구조인 $CuInS_{2}$ 박막으로 전환시켰다. 제작된 박막은 p-형이었고 저항률은$0.03{\sim}0.007{\Omega}cm$였으며, Hall 이동도는 $0.07{\sim}0.1cm^{2}V^{-1}S^{-1}$ 그리고 Hall 농도는 $10^{20-21}cm^{-3}$이었다.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• 마이크로전자및패키징학회지
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• 제25권2호
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• pp.49-53
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• 2018

최근 유연 소자, 투명 소자, MEMS 소자와 같은 다양한 소자를 결합하는 시스템 집적화 기술이 많이 개발되고 있다. 이러한 다종 소자 시스템 제조 기술의 핵심 공정은 칩 또는 웨이퍼 레벨의 접합 공정, 기판 연삭 공정, 그리고 박막 기판 핸들링 기술이라 하겠다. 본 연구에서는 Si 기판 연삭 공정이 투명 박막 트랜지스터나 유연 전극 소재로 적용되는 산화주석 박막의 전기적 성질에 미치는 영향을 분석하였다. Si 기판의 두께가 얇아질수록 Si d-spacing은 감소하였고, Si 격자 내에 strain이 발생하였다. 또한, Si 기판의 두께가 얇아질수록 산화주석 박막 내 캐리어 농도가 감소하여 전기전도도가 감소하였다. 얇은 산화 주석 박막의 경우 전기전도도는 두꺼운 산화 주석 박막보다 낮았으며 Si 기판의 두께에 의해 크게 변하지 않았다.