• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.138-144
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• 1995

It is commonly believed that high permittivity materials will be necessary for future high density Gbit DRAMs. In a first part, we explain the choice of SrTiO3 by ECR MOCVD for Gbit-scale DRAMs. In a second part, after describing the ECR MOCVD system and presenting the requirements SrTiO3 thin films should meet for use in Gbit-scale DRAMs, the physical and electrical properties of srTiO3 thi film prepared by ECR MOCVD are then studied. A stacked capacitor technology, suitable for use in 1 Gbit DRAM, and comprising high permittivity SrTiO3 thin films prepared by ECR MOCVD at $450^{\circ}C$ on electron beam and RIE patterned RuO2/TiN storage nodes is finally described.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.117-123
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• 1992

$Pt-SnO_{2-x}$ thin film sensing devices has been fabricated by thermal oxidation of stacked Pt-Sn thin film on the heater. The thickness of Sn thin film deposited by thermal evaporation was $4000{\AA}$ and the thickness of Pt deposited by D. C. sputtering on Sn thin film was $14{\sim}71{\AA}$ range. The XRD analysis show that the $Pt-SnO_{2-x}$ thin films are formed by grains with a diameter of about $200{\AA}$ randomly connected and the crystalline phase of the thin films are preferentally oriented in the (110) direction. $Pt-SnO_{2-x}$ thin film device (Pt thickness : $43{\AA}$) to 6000 ppm CO shows the sensitivity of 80% and high selectivity to CO. And the operating temperature and the thermal oxidation temperature of $Pt-SnO_{2-x}$ thin film device with high sensitivity to CO were $200^{\circ}C$ and $500^{\circ}C$, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.1
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• pp.8-13
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• 2020

Stress is the main cause of warpage failure of very thin substrates with thickness of several hundred ㎛, such as IC packages. Stress usually results from differences in crystal structures and corresponding thermal expansion coefficients when depositing different substances on a substrate. In this study, the behaviors of stress occurring in substrates were numerically analyzed by the thin-film pattern of the rectangles stacked on the substrates. First, the substrate displacement was obtained and the substrate strain and stress were obtained using it. When the tensile force is concentrated at the edge of the thin film pattern, normal and shear stresses are generated around the edge of the thin film pattern. Normal stress occurs near the edges of the thin film pattern and the vertexes. Shear stress also occurs around the edge of the thin film pattern, but unlike normal stress, it does not appear near the vertexes. It was also confirmed that the magnitude and direction of shear stress are changed around the edge. When edge forces of thin-film pattern are equal, the normal stress was about 10 times larger than the shear stress. This indicates that normal stress is the biggest cause of warpage failure.

• Transactions on Electrical and Electronic Materials
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• v.11 no.2
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• pp.73-76
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• 2010

The copper indium disulfide ($CuInS_2$) thin film was manufactured using sputtering and thermal evaporation methods, and the annealing with sulfurization process was used in the vacuum chamber to the substrate temperature on the glass substrate, the annealing temperature and the composition ratio, and the characteristics thereof were investigated. The $CuInS_2$ thin film was manufactured by the sulfurization of a soda lime glass (SLG) Cu/In/S stacked [1] elemental layer deposited on a glass substrate by vacuum chamber annealing [2] with sulfurization for various times at a temperature of substrate temperature of $200^{\circ}C$. The structure and electrical properties of the film was measured in order to determine the optimum conditions for the growth of $CuInS_2$ ternary compound semiconductor $CuInS_2$ thin films with a non-stoichiometric composition. The physical properties of the thin film were investigated under various fabrication conditions [3,4], including the substrate temperature, annealing temperature and annealing time by X-ray diffraction (XRD), field Emission scanning electron microscope (FE-SEM), and Hall measurement systems. [5] The sputtering rate depending upon the DC/RF power was controlled so that the composition ratio of Cu versus In might be around 1:1, and the substrate temperature affecting the quality of the film was varied in the range of room temperature (RT) to $300^{\circ}C$ at intervals of $100^{\circ}C$, and the annealing temperature of the thin film was varied RT to $550^{\circ}C$ in intervals of $100^{\circ}C$.

• Current Photovoltaic Research
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• v.7 no.1
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• pp.1-8
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• 2019

The $Cu(In,Ga)Se_2$ (CIGS) thin film obtained by two-step process (metal deposition and Se annealing) has a rough surface morphology and many voids at the CIGS/Mo interface. To solve the problem a precursor that contains Se was employer by depositing a (In,Se)/(Cu,Ga) stacked layer. We devised a two-step annealing (vacuum pre-annealing and Se annealing) for the precursor because direct annealing of the precursor in Se environment resulted in the small grains with unwanted demarcation between stacked layers. After vacuum pre-annealing up to $500^{\circ}C$ the CIGS film consisted of CIGS phase and secondary phases including $In_4Se_3$, InSe, and $Cu_9(In,Ga)_4$. The secondary phases were completely converted to CIGS phase by a subsequent Se annealing. A void-free CIGS/Mo interface was obtained by the two-step annealing process. Especially, the CIGS film prepared by vacuum annealing $450^{\circ}C$ and subsequent Se annealing $550^{\circ}C$ showed a densely-packed grains with smooth surface, well-aligned bamboo grains on the top of the film, little voids in the film, and also little voids at the CIGS/Mo interface. The smooth surface enhanced the cell performance due to the increase of shunt resistance.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.653-655
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• 2003

Using stacked organic gate insulators and active layer of pentacene deposited at elevated temperatures, pentacene-based organic thin-film transistors(OTFTs) with improved electrical characteristics have been fabricated. Stacked PVP(Polyvinylphenol)-polystyrene gate insulators could compensate the demerits and take advantage of the merits of each other [1]. Also, for the better device performance, moderate substrate heating and high deposition rate of pentacene active layer was adopted [2, 3].

• Macromolecular Research
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• v.14 no.1
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• pp.38-44
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• 2006

Vacuum deposited copper phthalocyanine (CuPc) was placed as a thin interlayer between indium tin oxide (ITO) electrode and a hole transporting layer (HTL) in a multi-layered, organic, light-emitting diode (OLEOs). The well-stacked CuPc layer increased the stability and efficiency of the devices. Thermal annealing after CuPc deposition and magnetic field treatment during CuPc deposition were performed to obtain a stacked-CuPc layer; the former increased the stacking density of the CuPc molecules and the alignment of the CuPc film. Thermal annealing at about 100$^{circ}C$ increased the current flow through the CuPc layer by over 25$\%$. Surface roughness decreased from 4.12 to 3.65 nm and spikes were lowered at the film surface as well. However, magnetic field treatment during deposition was less effective than thermal treatment. Eventually, a higher luminescence at a given voltage was obtained when a thermally-annealed CuPc layer was placed in the present, multi-layered, ITO/CuPc/NPD/Alq3/LiF/AI devices. Thermal annealing at about 100$^{circ}C$ for 3 h produced the most efficient, multi-layered EL devices in the present study.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.78-82
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• 1994

Single-phase $CuInS_{2}$ thin film were prepared by E-beam deposition and the effects of its annealing were investigated. The S/In/Cu was stacked from S, In and Cu by EBE method and then, In the nitrogen atmosphere, the stacked layer were annealed to convert chalcopyrite $CuInS_{2}$ thin films. and that result we obtained p-type Chalcopyrite $CuInS_{2}$ thin films, Its resistivity was $0.03{\sim}0.007{\Omega}cm$, Hall mobility was $0.07{\sim}0.1cm^{2}V^{-1}S^{-1}$ and Hall concentration was $10^{20-21}cm^{-3}$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.49-53
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• 2018

Recently, technologies for integrating various devices such as a flexible device, a transparent device, and a MEMS device have been developed. The key processes of heterogeneous device manufacturing technology are chip or wafer-level bonding process, substrate grinding process, and thin substrate handling process. In this study, the effect of Si substrate grinding process on the electrical properties of tin oxide thin films applied as transparent thin film transistor or flexible electrode material was investigated. As the Si substrate thickness became thinner, the Si d-spacing decreased and strains occurred in the Si lattice. Also, as the Si substrate thickness became thinner, the electric conductivity of tin oxide thin film decreased due to the lower carrier concentration. In the case of the thinner tin oxide thin film, the electrical conductivity was lower than that of the thicker tin oxide thin film and did not change much by the thickness of Si substrate.