• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.73-78
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• 1991

In this study of stacked type film chip capacitor, the important parameters are heat-treated temperature, pressure and time. We measured the temperature dependence of dielectric properties and dissipation factor and the frequency dependence of dielectric properties, dissipation factor, ESR(Equivalent Series Resistance) and impedance in stacked type film capacitor. As a result, the best conditions of heat-treated temperature, pressure and time were proved to be 130$^{\circ}C$, 10kg/$\textrm{cm}^2$ and 3hrs, respectively.

• Progress in Superconductivity and Cryogenics
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• v.2 no.1
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• pp.40-44
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• 2000

The round HTS wire is easier to handle than the rectangular HTS tape. This paper describes the coupling losses of the round HTS wires by finite element method. Effect of the round HTS wire are considered. Two types of Filaments arrangement, stacked filament and radial filaments, are considered. Calculation results show that coupling losses of the round HTS wire vary only a little with the direction of external magnetic field.

• ETRI Journal
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• v.28 no.6
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• pp.796-798
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• 2006

This letter proposes a tapered stacked microstrip antenna for application in small unmanned aerial vehicles (UAVs), which has advantages in mountainous terrains. With its tapered structure and increased bandwidth designed to operate at the resonance frequency of 2.4 GHz, the proposed antenna improves directivity, accuracy, and precision of small UAVs. The test flight results show the proposed tapered antenna has a three times higher impedance capability of 350 MHz based on VSWR<2. The transmission pattern is also more reliable than that of previous antenna designs.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.250-253
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• 2003

Rise of the current level at power applications, such as, transformer, motor and power cable, need for using stacked HTS tapes. In this paper, we measured losses of the stacked HTS tapes. Three different types of the stacks which were made of 2 tapes, 3 tapes and 4 tapes, were tested Perpendicular magnetic field was applied to the HTS stacks as the external magnetic field. Effects of the gap between HTS tapes were examined.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.909-911
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• 2002

Rises of current level at power applications, such as transformer, motor, power cable need for using stacked HTS tapes. In this paper, we measured rises of temperature and tap voltage in 4-stacked HTS tapes under over-current condition. We measured 4-stacked HTS tapes properties under over-current condition with a little temperature rise as well as a large temperature rise. Rises of temperature and tap voltage are measured by using E-type thermocouples and voltage taps, respectively. According to the results of measurement, rises of tap voltage under over-current condition with a large temperature rises depends on rises of temperature.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.314-319
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• 2015

The conventional geometry of a plate microstrip resonator is made up of a single metallic patch, which is printed on a monolayer dielectric substrate. Its arrangement is simple and easy to make, but it is limited in its functional abilities. Many searches have been realized to improve the bandwidth and the gain of the microstrip resonators. Among the various configurations proposed in the open literature, the stacked geometry seems to be very promising. By appropriate design, it is able to provide the operation in dual frequency mode, wide bandwidth enough and high gain. The theoretical investigations of structures composed of two stacked anti-reflection coatings, enhanced metallic coatings are available in the literature, however, for the stacked configurations involving three metallic coatings or more, not to exact or approximate analysis was conducted due to the complexity of the structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.344.1-344.1
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• 2016

Recently, graphene has shown great characteristic of electrical conductivity, strength, and elasticity. However, due to edge unstable and metallic properties, it is difficult to use as a semiconductor devices. The solution of such problems has been sought a way to use the boron nitride in a stacked layer structure. By graphene and boron nitride stacked layer structure on silicon substrate, the electron mobility is improved and deteriorated results in semiconductor properties. In this study, to make layered structure, we developed direct synthesis method for graphene on boron nitride. By using Raman technique, the directly stacked layer structure is in good agreement with measurements on each of the attributes.

• Journal of the Earthquake Engineering Society of Korea
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• v.22 no.6
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• pp.345-352
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• 2018

It is inevitable to use the distinct element method in the analysis of structural dynamics for stacked stone pagoda system. However, the experimental verification of analytical results produced by the discrete element method is not sufficient yet, and the theory of distinct element method is not universal in Korea. This study introduces how to model the stacked stone pagoda system using the distinct element method, and draws some considerations in the seismic analysis procedures. First, the rocking mode and sliding mode are locally mixed in the seismic responses. Second, the vertical stiffness and the horizontal stiffness on the friction surface have the greatest influence on the seismic behavior. Third, the complete seismic analysis of stacked stone pagoda system requires a set of the horizontal, vertical, and rotational velocity time histories of the ground. However, earthquake data monitored in Korea are limited to acceleration and velocity signals in some areas.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).