• 제목/요약/키워드: stacked

검색결과 1,139건 처리시간 0.025초

레이저 결정화 방법을 적용한 3차원 적층 CMOS 인버터의 전기적 특성 개선 (Electrical characteristics of 3-D stacked CMOS Inverters using laser crystallization method)

  • 이우현;조원주;오순영;안창근;정종완
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 추계학술대회 논문집
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    • pp.118-119
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    • 2007
  • High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

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고성능 PMOSFET을 위한 Ni-silicide와 p+ Source/drain 사이의 Barrier Height 감소 (Reduction of Barrier Height between Ni-silicide and p+ Source/drain for High Performance PMOSFET)

  • 공선규;장잉잉;박기영;이세광;정순연;신홍식;이가원;왕진석;이희덕
    • 한국전기전자재료학회논문지
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    • 제22권6호
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    • pp.457-461
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    • 2009
  • In this paper, barrier height between Ni-silicide and source/drain is reduced utilizing Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. It is shown that the barrier height is decreased by Pd incorporation and is dependent on the Pd thickness. Therefore, Ni-silicide using the Pd stacked structure is promising for high performance nano-cale PMOSFET.

3D 적층 IC제조를 위한 웨이퍼 휨 측정법 (Novel Wafer Warpage Measurement Method for 3D Stacked IC)

  • 김성동;정주환
    • 반도체디스플레이기술학회지
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    • 제17권4호
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    • pp.86-90
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    • 2018
  • Standards related to express the non-flatness of a wafer are reviewed and discussed, for example, bow, warp, and sori. Novel wafer warpage measurement method is proposed for 3D stacked IC application. The new way measures heat transfer from a heater to a wafer, which is a function of the contact area between these two surfaces and in turn, this contact area depends on the wafer warpage. Measurement options such as heating from room temperature and cooling from high temperature were experimentally examined. The heating method was found to be sensitive to environmental conditions. The cooling technique showed more robust and repeatable results and the further investigation for the optimal cooling condition is underway.

혼성 표본 추출과 적층 딥 네트워크에 기반한 은행 텔레마케팅 고객 예측 방법 (A Method of Bank Telemarketing Customer Prediction based on Hybrid Sampling and Stacked Deep Networks)

  • 이현진
    • 디지털산업정보학회논문지
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    • 제15권3호
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    • pp.197-206
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    • 2019
  • Telemarketing has been used in finance due to the reduction of offline channels. In order to select telemarketing target customers, various machine learning techniques have emerged to maximize the effect of minimum cost. However, there are problems that the class imbalance, which the number of marketing success customers is smaller than the number of failed customers, and the recall rate is lower than accuracy. In this paper, we propose a method that solve the imbalanced class problem and increase the recall rate to improve the efficiency. The hybrid sampling method is applied to balance the data in the class, and the stacked deep network is applied to improve the recall and precision as well as the accuracy. The proposed method is applied to actual bank telemarketing data. As a result of the comparison experiment, the accuracy, the recall, and the precision is improved higher than that of the conventional methods.

1세대 선재와 2세대 선재의 혼합 적층에 따른 자화손실 특성 (Magnetization loss of Hybrid Multi-Stacked wire made of 1G wires and 2G wires)

  • 임형우;이용석;이희준;차귀수
    • 한국초전도ㆍ저온공학회논문지
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    • 제9권1호
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    • pp.57-60
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    • 2007
  • Superconducting electric power devices need to stack HTS wires to increase the current carrying capacity. Uniform multi-stacked wires(UMS) which were made of the same HTS wires have been used. This paper shows the magnetization loss of hybrid multi-stacked(HMS) wire made of BSCCO wires and YBCO wires. Five HMS wires, YB(YBCO-BSCCO), YYBB. YBYB, YBBY and BYYB, were made and tested. Magnetization losses of each UMS wire were compared with corresponding HMS wire. Test results show that magnetization losses per unit length of HMS wire are between the corresponding UMS BSCCO wire and HMS YBCO wire below critical magnetic field. Above the critical magnetic field, magnetization losses of HMS wires are larger than that of corresponding both VMS wires.

High-sensitivity NIR Sensing with Stacked Photodiode Architecture

  • Hyunjoon Sung;Yunkyung Kim
    • Current Optics and Photonics
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    • 제7권2호
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    • pp.200-206
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    • 2023
  • Near-infrared (NIR) sensing technology using CMOS image sensors is used in many applications, including automobiles, biological inspection, surveillance, and mobile devices. An intuitive way to improve NIR sensitivity is to thicken the light absorption layer (silicon). However, thickened silicon lacks NIR sensitivity and has other disadvantages, such as diminished optical performance (e.g. crosstalk) and difficulty in processing. In this paper, a pixel structure for NIR sensing using a stacked CMOS image sensor is introduced. There are two photodetection layers, a conventional layer and a bottom photodiode, in the stacked CMOS image sensor. The bottom photodiode is used as the NIR absorption layer. Therefore, the suggested pixel structure does not change the thickness of the conventional photodiode. To verify the suggested pixel structure, sensitivity was simulated using an optical simulator. As a result, the sensitivity was improved by a maximum of 130% and 160% at wavelengths of 850 nm and 940 nm, respectively, with a pixel size of 1.2 ㎛. Therefore, the proposed pixel structure is useful for NIR sensing without thickening the silicon.

빗살형 전극을 이용한 적층 세라믹 박판 작동층 IDEAL의 설계/제조/성능시험 (Design/Manufacturing/Performance-Test of Stacked Ceramic Thin Actuation Layer IDEAL Using Interdigitated Electrodes)

  • 이제동;박훈철;구남서;윤영수;윤광준
    • 한국세라믹학회지
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    • 제41권3호
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    • pp.216-220
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    • 2004
  • 본 논문은 압전세라믹의 압전상수 d$_{33}$ 를 이용한 적층 세라믹 박판 작동층 IDEAL (InterDigitated Electrode Actuation Layer)의 개발에 관한 것이다. 대부분의 박판 압전 작동층은 압전상수 d$_{31}$ 효과를 이용하고 있다. 현재 개발된 압전작동기의 성능을 향상시키기 위해 많은 연구가 수행 중에 있으며, 그 중 한 방법이 압전상수 d$_{33}$ 를 이용하는 방법이다. 압전세라믹의 압전상수 d$_{33}$ 는 압전상수 d$_{31}$ 보다 일반적으로 두배 정도이기 때문에 d$_{33}$ 작동 효과를 활용하면 작동기의 성능을 향상시킬 수 있다. 미국 MIT에서 개발된 AFC와 NASA Langley 연구소 연구팀이 개발한 LaRC-MFC$^{TM}$는 d$_{33}$ 작동 효과를 활용하였으나 빗살형 전극이 작동층 상하 표면에 부착되어 있어 완전한 d$_{33}$ 작동 효과를 활용하였다고 볼 수 없다. 본 논문에서는 빗살형 전극을 세라믹 층간에 삽입한 적층형 세라믹 박판 작동층을 설계하고 제작하였다. 제작된 작동층의 작동 스트레인을 측정하였고 LaRC-MFC$^{TM}$의 작동 스트레인과 비교한 결과, 본 연구에서 개발한 박판 세라믹 작동층이 15% 이상의 작동 스트레인을 발생시킬 수 있음을 확인하였다.

광대역 특성을 위한 적층형 정사각형 링 마이크로스트립 슬롯 안테나 (Stacked Square-Ring Microstrip Slot Antenna for Broadband Characteristics)

  • 이선기;최준호;김영식
    • 한국전자파학회:학술대회논문집
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    • 한국전자파학회 2000년도 종합학술발표회 논문집 Vol.10 No.1
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    • pp.319-323
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    • 2000
  • A method for miniaturization of microstrip patch antenna without degrading its radiation characteristics is investigated. The ring geometry introduces additional parameters to the antenna that can be used to control its resonance frequency and bandwidth. For a single square ring increasing the size of patch decreases the resonance frequency and bandwidth. To match the antenna to a transmission line and also enhance its bandwidth. the square ring patch is stacked by a square ring patch. The computed results are compared with experiment and good agreement is obtained.

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1.8GHz 대역의 저전압용 CMOS RF하향변환 믹서 설계 (A 1.8GHz Low Voltage CMOS RF Down-Conversion Mixer)

  • 김희진;이순섭;김수원
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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    • pp.61-64
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    • 2000
  • This paper describes a RF Down-Conversion Mixer for mobile communication systems. This circuit achieves low voltage operation and low power consumption by reducing stacked devices of conventional gilbert cell mixer. In order to reduce stacked devices, we use source-follower structure. The proposed RF Down-Conversion mixer operates up to 1.85GHz at 1.5V power supply with 0.25um CMOS technology and consumes 2.2mA.

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