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http://dx.doi.org/10.4313/JKEM.2009.22.6.457

Reduction of Barrier Height between Ni-silicide and p+ Source/drain for High Performance PMOSFET  

Kong, Sun-Kyu (충남대학교 전자공학과)
Zhang, Ying-Ying (충남대학교 전자공학과)
Park, Kee-Young (충남대학교 전자공학과)
Li, Shi-Guang (충남대학교 전자공학과)
Jung, Soon-Yen (충남대학교 전자공학과)
Shin, Hong-Sik (충남대학교 전자공학과)
Lee, Ga-Won (충남대학교 전자공학과)
Wang, Jin-Suk (충남대학교 전자공학과)
Lee, Hi-Deok (충남대학교 전자공학과)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.22, no.6, 2009 , pp. 457-461 More about this Journal
Abstract
In this paper, barrier height between Ni-silicide and source/drain is reduced utilizing Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. It is shown that the barrier height is decreased by Pd incorporation and is dependent on the Pd thickness. Therefore, Ni-silicide using the Pd stacked structure is promising for high performance nano-cale PMOSFET.
Keywords
Ni-silicide; Pd stacked structure; Barrier height; High performance PMOSFET;
Citations & Related Records
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