• Journal of Sensor Science and Technology
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• v.14 no.2
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• pp.96-100
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• 2005

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of $5.51{\times}10.5{\Omega}{\cdot}cm^{2}$ after annealing in an $N_{2}$ ambient at $700^{\circ}C$ for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about $10^{2}$. The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.759-762
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• 2006

A simple SPICE model for the description of the on-current of low-temperature poly-silicon thin film transistors is proposed. By employing constant mobility, $V_GS$ dependent alpha parameter, and exponential kink effect, very good agreements between the model and measurement were obtained.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.314-317
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• 2000

In order to analyze the characteristics of complicated TFT-LCD (Thin Film Transistor-Liquid Crystal Display) circuits, it is indispensible to use simulation programs. In this study, we present a systematic method of extracting the input parameters of poly-Si TFT for Spice simulation. This method is applied to two different types of poly-Si TFTs fabricated in our group with good results. Among the Spice simulators, Pspice has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT model on the Pspice simulator, which would contribute to efficient simulations of poly-Si TFT-LCD pixels and arrays.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.43-45
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• 2003

소프트웨어 공학이 소프트웨어 시스템에 관한 방법론, 기술 및 툴 등의 유지보수와 개발에 중점을 두어 왔는데 최근에는 프로세스 개선과 프로세스 능력수준의 향상에 초점을 두는 방향으로 발전하면서 CMM 및 SPICE 활동이 증가하고 있다. 이와 같은 심사기법은 대규모의 회사에서 주로 시행되고 있어서 중소규모의 조직을 위한 간략한 심사기법의 도입이 요구되는 있는 상황이다. 본 논문에서 제시하는 심사기법은 CMM 심사를 위한 KPA 설문서의 rating 방법을 응용한 것으로서 SPICE 심사를 받은 국내 기업 중 일부 회사를 대상으로 하였다. 이 방법론에 대한 신뢰성의 평가는 아직 미흡한 상황이다. 이를 위해서 통계학적 접근방법을 도입하였는데 사용된 통계 기법은 상환계수를 통한 가설검정이다. 그 결과 성숙도 설문서(MQ) 선정모델의 적합성을 통계적 기법을 통해서 검증하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1063-1066
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• 2002

An equivalent circuit for the superconductor flux flow transistor(SFFT) was combined with high temperature cooling device, based on the analogy between thermal and electrical variables using the high-temperature superconductor(HTS), is proposed. The device is composed of parallel weak links with a nearby magnetic control line. A model has been developed that is based on solving the equation of motion of Abrikosov vortices subject to Lorentz viscous and pinning forces as well as magnetic surface barriers. The use of thermal models the global performance of thermal cooling circuit and signal system to be checked by using electrical circuit analysis programs such as SPICE.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.76-85
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• 1993

This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.82-84
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• 1993

A method for simulating general characteristics and temperature characteristics of magnetizing fixture coil of the capacitor discharge impulse magnetizer-magnetizing fixture system using SPICE is presented. This method has been developed which can aid the design, understanding and inexpensive, time-saving of magnetizing circuit. As the detailed characteristics of magnetizing circuit can be obtained, the efficient design of the magnetizing circuit which produce desired magnet will be possible using our SPICE modeling. Especially, The knowledge of the temperature of the magnetizing fixture is very important to forecast the characteristics of the magnetizing circuits tinder different conditions. The capacitor voltage was not raised above 810[V] to protect the magnetizing fixture from excessive heating. The temperature estimation method uses multi-lumped model with equivalent thermal resistance and thermal capacitance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.700-709
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• 1988

A new technique is proposed for switch-level logic simulation for NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance and the device configuration ratio, the polynomial coefficients being so determined as to best fit the SPICE simuladtion results for a given fabrication process. This approach can easily and accurately be extened to the case of multiple input transitions. The simulation results show that proposed method can predict the delay times within 5% error and with a speed up by a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.156-163
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• 1994

A new circuit simulator for submicron MOS desings was developed by enhancing SPICE3. The minimum conductance stepping, source stepping and pseudo transient methods are applied to improve the convergence. and SECSPICE uses the variation rate of the node volgage in the timestep algorithm. The modified BSIM model was implemented in SECSPICE for submicron MOS designs. And it gives the powerful user environments such as graphic user environments. As the results of test using real measured device data and circuits used in real production desing, we found it gave more accurage results than BSIM and the execution speed was 1.5~2.8 times faster than SPICE3.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.3
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• pp.204-210
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• 2000

This paper proposes a new reactive-power compensator composed of a soft-switching current-source inverter. The compensator consists of 3-Phase IGBT bridge, dc reactor, and a resonant circuit. The resonant circuit offers the IGBT bridge to have PWM operation with minimal switching losses. A theoretical analysis and computer simulation with Is-Spice were done to verify the operation of the proposed system. Also a acaled-model of the system was built and tested for verifying the feasibility of proposed system.