• Title/Summary/Keyword: speed error rate

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A Numerical Analysis for Prediction of Flow Rate of the Motor Cooling Fan (전동기 냉각팬의 유량예측을 위한 수치해석)

  • Lee, Sang-Hwan;Kang, Tae-In;Ahn, Chel-O;Seo, In-Soo;Lee, Chang-Joon
    • 유체기계공업학회:학술대회논문집
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    • 2005.12a
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    • pp.670-677
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    • 2005
  • In this study, we analyzed the three dimensional unsteady flow field around the motor cooling fan using the unsteady lifting surface theory. We obtained the flow rate for various geometries of fan from the calculated results of velocity field. For the data of design parameter and rotating speed(rpm) of the fan, we can predict the flow rate of the motor cooling fan with thin thickness through numerical analysis without the experimental data of the free stream velocity which is a boundary condition of flow field. the numerical results showed the flow rate within 10% of error in comparison with experimental results. The radial fans, which are often used as internal motor fan were also investigated with the same procedure.

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Reliability Analysis Method for Repeated UT Measurement Data in Nuclear Power Plants (원전 배관의 반복 측정 데이터에 대한 신뢰도 분석 방법)

  • Yun, Hun;Hwang, Kyeong-Mo
    • Corrosion Science and Technology
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    • v.12 no.3
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    • pp.142-148
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    • 2013
  • Safety is a major concern in Nuclear Power Plants (NPPs). Piping systems in NPPs are very complex and composed of many components such as tees, elbows, expanders and straight pipes. The high pressure and high temperature water flows inside piping components. As high speed water flows inside piping, the pipe wall thinning occurs in various reasons such as FAC (Flow Accelerated Corrosion), LDIE (Liquid Droplet Impingement Erosion) and Flashing. To inspect the wall thinning phenomenon and protect the piping from damages, piping components are checked by UT measurement in every overhaul. During every overhaul, approximately 200~300 components (40,000~60,000 UT data) are examined in NPPs. There are some methods from EPRI for evaluating wear rate of components. However, only few studies have been conducted to find out the raw data reliability for the wear rate evaluation. Securing the reliable raw data is the key factor for a reasonable evaluation. This paper suggests the reliability analysis method for the repeatedly measured data for wear rate evaluation.

Performance of Doppler Compensation Technique for Railway Communication System (철도 통신 시스템에서의 도플러 보상기법의 성능)

  • Park, Jae Jung;Kim, Yoon Hyun;Kim, Jin Young;Yang, Jae Soo
    • Journal of Satellite, Information and Communications
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    • v.7 no.3
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    • pp.35-40
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    • 2012
  • Since the opening of Korean high-speed rail, KTX in 2004, the use of trains in Korea soared. Improved rail technology, as well as the speed of the train was developed. However, the development of the train speed raised new issues of Doppler effect and this effect compensation. Depending on the speed of communication target, Doppler effect generates frequency shifting and this effect leads to a distortion of the signal. For this reason, the Doppler effect adversely affect the communication performance. Therefore, the Doppler effect problem must be solved for the railway wireless communication. In this paper, we present technique of compensation for the Doppler effect that occurs in high-speed railway communication and simulation result.

Three-Parallel Reed-Solomon based Forward Error Correction Architecture for 100Gb/s Optical Communications (100Gb/s급 광통신시스템을 위한 3-병렬 Reed-Solomon 기반 FEC 구조 설계)

  • Choi, Chang-Seok;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.48-55
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    • 2009
  • This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

Line-of-Sight Rate for Off-axis Seeker on a 2-axis Gimbal (2축 김발 위에 장착된 비축탐색기를 위한 시선각속도 계산)

  • Kim, Jeong-Hun;Park, Kuk-Kwon;Ryoo, Chang-Kyung
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.47 no.3
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    • pp.187-194
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    • 2019
  • The off-axis Infra-Red(IR) seeker is mounted on the nose cone side of the anti-air high speed missile to alleviate thermal shield effect due to aerodynamic heating. The seeker output can not be regarded as the Line-of-Sight(LOS) rate any more as missile's roll motion to keep the target tracking is associated. In this paper, we propose a method to calculate the LOS rate for off-axis seeker on a 2-axis gimbal. Firstly, true LOS rate equations are analytically derived but not implementable because boresight error rate is not measurable. And then the first order lag approximation to obtain boresight error rate is proposed. The proposed LOS rate calculation method can compensate the coupling effect by considering the rotations of missile and gimbal. The performance of the proposed method is verified via full nonlinear 6-DOF(Degree of Freedom) simulations.

Factors Influencing Farm-Gate Shrimp Prices in Thailand: An Empirical Study Using the Time Series Method

  • MUANGSRISUN, Donlathorn;JATUPORN, Chalermpon;SEERASARN, Nareerut;WANASET, Apinya
    • The Journal of Asian Finance, Economics and Business
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    • v.8 no.5
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    • pp.769-775
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    • 2021
  • The objective of this research was to analyze the factors influencing the farm-gate shrimp prices in Thailand using monthly time series from January 2001 to December 2019. The econometric methodology was employed to satisfy the purpose, consisting of the cointegration test for revealing the long-run relationship and equilibrium elasticity between the variables as well as the error correction model for detecting speed adjustment to shock responses. The empirical results revealed that (1) the export shrimp prices, shrimp production in the country, and shrimp export volume indicated a long-run relationship running to the farm-gate shrimp prices in Thailand with the size of equilibrium elasticity equal to 1.083%, -0.256%, and 0.123, respectively, and (2) the farm-gate shrimp prices in Thailand would adjust to the equilibrium line with a speed equal to 20.147% if there was any kind of incident or shock which caused the relationship to deviate from the equilibrium point. There was no relationship in terms of global shrimp prices and the exchange rate for farm-gate shrimp prices in Thailand. The recommendations should emphasize the varieties of shrimp products for export to other countries beyond the main trading markets nowadays to reduce risks and fluctuations in the export prices of shrimp products.

The Optimal Letter Spacing and Line Spacing of Korean on the Visual Display (VDT 화면에서의 한글 자간간격과 행간간격에 관한 연구)

  • 황우상;부진후;이동춘
    • Proceedings of the ESK Conference
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    • 1998.04a
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    • pp.161-166
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    • 1998
  • In this study, the optimum criteria of space between the lines and the letters which could largely affect the legibility were found by the experiment and were presented as guidelines to design Korean VDT screens. Since the experiment was designed to test the human performance based on the VDT screen design, searching speed (S.S) and error rate (E) were used as the criteria of performance, and CFF value was measured to evaluate user's visual fatigue. The EOG value was also measured for the visual restriction during the experiment for the space between the lines and letters.

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A Modeling of CMOS Inverter for Maximum Power Dissipation Prediction (CMOS 인버터의 최대 전력소모 예측을 위한 모델링)

  • 정영권;김동욱
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1057-1060
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    • 1998
  • Power Dissipation and circuit speed become the most importance parameters in VLSI system maximum power dissipation for VLSI system design. We remodeled CMOS inverter according to the operating region, saturation region or linear regin, and calculate maximum power dissipation point of CMOS inverter. The result of proposed maximum power dissipation model compared with those from SPICE simulation which results that the proposed maximum power dissipation model has the error rate within 10% to SPICE simulation.

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A study on the implementation of the fault-tolerant digital filter using self-checking pulse rate residue arithmetic circuits. (자기검사(自己檢査) 펄스열(列) 잉여수연산회로(剩餘數演算回路)를 이용한 폴트 토러런트 디지탈 필타의 구성(構成)에 관한 연구(硏究))

  • Kim, Moon-Soo;Chun, Koo-Chae
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1185-1187
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    • 1987
  • Digital systems are increasingly being used in the ranges of many control engineering. The residue number system offers the possibility of high speed operation and error correction. The compact self-checking pulse-train residue arithmetic circuit is proposed. A fault tolerant digital filter is practically implemented using these proposed circuits.

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Performance Analysis of Adaptive Equalization in the Frequency Selective Fading Channel (주파수 선택성 페이딩 채널에서 적응 등화기의 성능 분석)

  • 노재호;김남용;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.3
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    • pp.248-258
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    • 1991
  • In this paper, ISI cancellation capabilites in the frequency selective fading channels of the equalizer emplouing individual tap LMS(ITLMS) algorithm and of th equalizer using the lattice structure have been investigated through the computer simulations in terms of bit error rate and convergence speed.

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