• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.4
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• pp.230-236
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• 2022

In this paper, we propose an efficient concatenated code for both random and ISI errors on diffusion-based molecular communication channels. The proposed concatenated code was constructed by combining the ISI-mitigating code designed for ISI mitigation and the ISI-Hamming code strong against random errors, and the BER(bit error rate) performance was analyzed through simulation. In the case of the above M=1,200 channel environment, it was found that the error rate performance of the concatenated code follows the error rate performance of the ISI-mitigating code, which is strong against ISI, and follows the error rate performance of the ISI-Hamming code, which is strong against random errors, in the channel environment below M=600. In M=600~1,200, the concatenated code shows the best error rate performance among those of three codes, which is analyzed because it can correct both random errors and errors caused by ISI. In the following cases of below M=800, it can be seen that the error rate of the concatenated code and the ISI-mitigating code shows an error rate difference of about 1.0×10^-1 on average.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.8
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• pp.17-22
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• 2016

For the self-adaptive equalization of higher-order QAM systems, this paper proposes a new soft decision-directed (SDD) algorithm that opens the eye patterns quickly as well as significantly reducing the error level in the steady-state when it is applied to the initial equalization stage with completely closed eye patterns. The proposed method for M-QAM application minimized the computational complexity of the existing SDD by the symbol estimated based on the two symbols closest to the observation, and greatly simplified the soft decision independently of the QAM order. Furthermore, in the symbol estimating it increased the reliability of the estimates by applying the superior properties of the sigmoid function and avoiding the erroneous estimation of the threshold function. In addition, the initialization performance was improved when an error is generated to update the equalizer, weighting the symbol decision by the threshold function to the error, resulting in an extension of the range of error fluctuations. As a result, the proposed method improves remarkably the computational complexity and the properties of initialization and convergence of the traditional SDD. Through simulations for 64-QAM and 256-QAM under multipath channel conditions with additive noise, the usefulness of the proposed methods was confirmed by comparing the performance of the proposed 2-SDD and two forms of weighted 2-SDD with CMA.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.10-21
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• 2015

Cellular Network assisted device-to-device (D2D) communication has been growing to reduce the overload of eNodeB and mitigate the frequency shortage. However, by sharing the uplink frequency resource with the cellular network, the interference between cellular and D2D is increased. In this paper, we propose the advanced receiver based on soft decision to reduce the interference between cellular and D2D. The proposed receiver can suppress and cancel the interference by calculating the unbiased estimation value of interference signal using minimum mean square error (MMSE) or interference rejection combing (IRC) receiver. The interference signal is updated using soft information expressed by log-likelihood ratio (LLR). We perform a system level simulation based on the 20-MHz bandwidth of the 3GPP LTE-A system. Simulation results show that the proposed receiver can improve SINR, throughput and spectral efficiency compared to conventional receivers.

• Journal of Urban Science
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• v.6 no.2
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• pp.49-57
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• 2017

A new Fiber Bragg Grating (FBG) wavelength demodulation scheme is studied in the paper, which consists of an improved de-noising method and Gaussian fitting peak searching algorithm. The improved translational invariant wavelet without threshold adjust factor is proposed to get a better de-noising performance for FBG sensor signal and overcome the drawbacks of soft or hard threshold wavelets. In order to get a high wavelength demodulation precision of FBG sensor signal, this de-noising method is designed to combine with Gaussian fitting peak searching algorithm. The simulation results show that the wavelength maximum measurement error is lower than 1pm, and can get a much higher accuracy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.1-1
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• 2001

DRAM에서 셀 캐패시터의 누설 전류 영향을 고려하여 소프트 에러율을 예측하였다. DRAM의 동작 과정에서 누설 전류의 영향으로 셀 캐패시터는 전하량이 감소하고, 이에 따른 소프트 에러율을 DRAM의 각 동작 모드에 대하여 계산하였다. 누설 전류가 작을 경우에는 /bit mode가 소프트 에러에 취약했지만, 누설전류가 커질수록 memory 모드가 소프트 에러에 가장 취약함을 보였다. 실제 256M급 DRAM의 구조에 적용하여, 셀 캐패시턴스, bit line 캐패시턴스, sense amplifier의 입력 전압 감도들이 변화할 때 소프트 에러에 미치는 영향을 예측하였고, 이 결과들은 차세대 DARM 연구의 최적 셀 설계에 이용될 수 있다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.273-276
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• 2000

Recently, Turbo code has been considered for channel coding in IMT-2000(International Mobile Telecommunication-2000) system, because it offers better error correcting capability than the traditional convolution/viterbi coding . In this paper, a turbo code decoder for speech transmission in IMT-2000 system with frame size 192 bits, constrait length K=3, generator polynomials G(5,7) and code rate R=1/3 is designed using SOVA(Soft Output Viterbi Algorithm) and block interleaver

• Electrical & Electronic Materials
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• v.12 no.9
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• pp.57-63
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• 1999

SOI 구조의 MOSFET은 제조공정이 상대적으로 간단하며 CMOS 래치 업 현상이 일어나지 않고, soft error에 의한 회로의 오동작 가능성이 매우 낮은 이외에도 낮은 기생 정전용량 및 누설전류 특성을 가지므로 0.1 미크론 이하의 소자를 제작하는데 적합하여 저전압, 초고속 VLSI 설계에 적합한 소자로 각광받고 있다. 본고에서는 새로운 구조의 SOI MOSFET 구조들의 특성과 장, 단점을 검토하고 나아가 BJT(Bipolar Junction Transistor) 및 기타 소자들을 SOI 구조로 제작한 결과에 대해 간단히 검토함으로써 1999년 현재 SOI 기술의 현황을 소개하고자 한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.06a
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• pp.175-178
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• 2022

본 논문은 고차 계층 변조, 즉 계층 64QAM의 연판정 비트 검출을 위한 단순화된 연산 방법을 다룬다. 이는 기존 계층 변조의 연판정 비트, 즉 LLR(Log-Likelihood Ratio)값의 근사를 통해 불필요한 연산을 줄여 이에 필요한 지연시간을 줄일 수 있다. 또한 제안된 기법은 기존의 연판정 비트 검출 기법과 매우 유사한 비트 오류율(BER: Bit Error Rate) 성능을 유지하기 때문에 연판정 비트를 활용하는 방송 및 통신 시스템에 폭넓게 적용될 수 있을 것으로 기대한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1044-1051
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• 2010

In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple input multiple output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC (ESIC) algorithm with a multiple ordering technique in a very efficient way. As a result, the log likelihood ratio (LLR) values can be computed by using a very small set of candidate symbol vectors. The proposed method has been implemented with a $0.13{\mu}m$ CMOS technology for a $4{\times}4$ 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.