• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.863-866
• /
• 1999

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

• Journal of Institute of Control, Robotics and Systems
• /
• v.20 no.4
• /
• pp.443-448
• /
• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.2
• /
• pp.87-94
• /
• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• Journal of Satellite, Information and Communications
• /
• v.9 no.2
• /
• pp.23-27
• /
• 2014

In this paper, we propose a soft demapping method for 64-ary APSK in the DVB-S3 system. The proposed method in this paper uses the hard decision threshold (HDT) line for each constituent bit in a symbol, and calculates the soft bit information with the distance between the HDT line and the detected symbol. If the HDT lines are defined in a simple manner, the complexity to estimate soft information can be largely reduced compared with the maximum likelihood detection (MLD) which has an exponential complexity. By considering this, we first derive HDT lines for each constituent bit for a 64-APSK symbol, and propose a method to calculate soft bit information. We simulate the BER performance of the proposed scheme by using a turbo codes which requires soft-input-soft-output information, and compare it that of the MLD. The result show that the proposed scheme produces approximating performance to MLD with largely reduced complexity.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.445-454
• /
• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• Journal of Contemporary Eastern Asia
• /
• v.11 no.1
• /
• pp.21-29
• /
• 2012

The popularity of the Internet has affected international politics in many ways; however, it is seemingly overlooked by most scholars, and in particular, realists who view the Internet as low-politics. This article argues that the impact of the Internet on international politics should not be underestimated. By focusing on the capabilities of the Internet in general and P2P networks in particular, this paper shows how the Internet is able to disseminate soft power resources. This is demonstrated by an examination of the dissemination of Japanese soft power resources through BitTorrent. Finally, it is concluded that the Internet is a plausible agent for distributing the resources of soft power; however, once disseminated, soft power resources do not always transform into soft power. In the end, contextual conditions within states always apply.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.5C
• /
• pp.498-504
• /
• 2009

A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.2
• /
• pp.32-39
• /
• 1996

Hybrid decision decoding for the extended hamming codes without retransmission, which is a combination of hard and soft decision decoding, is proposed and its performance is analyzed in this paper. As results, hybsrid decision decoding shows a little bit higher residual bit error rate than soft decision decoding. However, as the size of the extended hamming code increases, the difference of th enumber of comparisons increases further. In addition, hybrid decision decoding shows almost same residual bit error rate as hard decision decoding with retrassmission and shows much lower residual bit error rate than hard decision decoding without retransmission.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.1
• /
• pp.128-136
• /
• 2008

In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.2
• /
• pp.55-61
• /
• 1999

A soft error rate (SER) simulator for DRAM was developed. In comparison to the other SER simulator using device simulator or Monte Carlo simulator, the proposed simulator substantially reduced the CPU time using an analytical model for the alpha-particle-induced charge collection. By analysing the soft error modes in DRAM, the bit-bar mode was identified as the main cause of soft error. Using the new SER simulator, SER of 256M DRAM was investigated and it was found that the storage capacitance had a 5fF margin.