• Journal of Korea Multimedia Society
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• v.9 no.12
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• pp.1700-1708
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• 2006

Since the most program execution time is consumed in a loop structure, extracting parallelism from loop programs is critical for the taster program execution. In this paper, we proposed data dependency removal method for a single loop. The data dependency removal method can be applied to uniform and non-uniform data dependency distance in the single loop. Procedure calls parallelisms with only a single loop structure or procedure call most of other methods are concerned with the uniform code within the uniform data dependency distance. We also propose an algorithm, which can be applied to uniform, non-uniform, and complex data dependency distance among the multiple procedures. We compared our method with conventional methods using CRAY-T3E for the performance evaluation. The results show that the proposed algorithm is effective.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1334-1337
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• 1997

A spacecraft attitude control ground hardware simulator development is discussed in the paper. The simulator is called KT/KARI HILSSAT(Hardware-In-the Loop Simulator Single Axis Testbed), and the main structure consists of a single axis bearing and a satellite main body model on the bearing. The single axis tabel as ans experimental hardware simulator that evaluates performance and applicability of a satellite before evolving and/or confirming a mew or and old control logic used in the KOREASAT is developed. Attitude control of spaceraft by using reaction wheel is performed.

• Proceedings of the IEEK Conference
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• summer
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• pp.334-338
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• 2004

In this paper, we suggest a new antenna structure for RFID(Radio Frequency IDentification) reader. Conventional RFID reader uses a loop antenna. The central area of a loop antenna shows a low magnetic field strength especially for the case of a large loop antenna diameter. We propose a parallel-fed multiple loop antenna. Simulation results and measured results show that we can adjust field distribution with the number of turns and diameter of an inner loop antenna to obtain a longer reading distance. Simulation results for the specific case of a proposed antenna structure show that at the center point of a proposed parallel-fed multiple loop antenna, the typical card area averaged magnetic field strength is 2.53A/m, which is higher than the case of a conventional type single loop antenna of 0.44A/m and the case of a series-fed multiple loop antenna of 0.96A/m when we drive with same source signal. We realized the antenna for the case of 13.56MHz RFID reader and the performance of reading distance was much more improved than the case of a conventional antenna.

• Journal of Microbiology
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• v.41 no.3
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• pp.239-247
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• 2003

The LRV1-4 capsid protein possesses an endoribonuclease activity that is responsible for the single site-specific cleavage in the 5' untranslated region (UTR) of its own viral RNA genome and the formation of a conserved stem-loop structure (stem-loop IV) in the UTR is essential for the accurate RNA cleavage by the capsid protein. To delineate the nucleotide sequences, which are essential for the correct formation of the stem-loop structure for the accurate RNA cleavage by the viral capsid protein, a wildtype minimal RNA transcript (RNA 5' 249-342) and several synthetic RNA transcripts encoding point-mutations in the stem-loop region were generated in an in vitro transcription system, and used as substrates for the RNA cleavage assay and RNase mapping studies. When the RNA 5' 249-342 transcript was subjected to RNase T1 and A mapping studies, the results showed that the predicted RNA secondary structure in the stem-loop region using FOLD analysis only existed in the presence of Mg$\^$2＋/ ions, suggesting that the metal ion stabilizes the stem-loop structure of the substrate RNA in solution. When point-mutated RNA substrates were used in the RNA cleavage assay and RNase T1 mapping study, the specific nucleotide sequences in the stem-loop region were not required for the accurate RNA cleavage by the viral capsid protein, but the formation of a stem-loop like structure in a region (nucleotides from 267 to 287) stabilized by Mg$\^$2＋/ ions was critical for the accurate RNA cleavage. The RNase T1 mapping and EMSA studies revealed that the Ca$\^$2＋/ and Mn$\^$2＋/ ions, among the reagents tested, could change the mobility of the substrate RNA 5' 249-342 on a gel similarly to that of Mg$\^$2＋/ ions, but only Ca$\^$2＋/ ions identically showed the stabilizing effect of Mg$\^$2＋/ ions on the stem-loop structure, suggesting that binding of the metal ions (Mg$\^$2＋/ or Ca$\^$2＋/) onto the RNA substrate in solution causes change and stabilization of the RNA stem-loop structure, and only the substrate RNA with a rigid stem-loop structure in the essential region can be accurately cleaved by the LRV1-4 viral capsid protein.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.921-926
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• 2014

In this paper, the characteristics of inset fed microstrip antenna loaded with CSLR(complementary single loop resonator) are studied. Effective permeability parameters of the SLR unit cell is retrieved from simulated scattering parameters, and structure parameters of the SLR unit cell are selected so that effective permeability is negative value at the operating frequency. The optimized inset fed microstrip antenna loaded with SLR for a $3{\times}3$ array in the ground plane of a conventional patch antenna is designed and simulation results of return loss and radiation pattern are shown. At resonant frequency 2.82 GHz, the overall dimension of the proposed antenna is reduced by approximately 56.8% compared to the conventional inset fed antenna. Simulation results are obtained by 3D FEM solver(Ansoft's HFSS).

• Journal of Power Electronics
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• v.14 no.6
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• pp.1334-1344
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• 2014

A novel single phase Phase-Locked Loop (PLL) is proposed in this paper to accurately and rapidly estimate the instantaneous phase angle of a grid. A conjugate rotating vector pair is proposed and defined to synthesize the single phase signal in the stationary reference frame. With this concept, the proposed PLL innovatively sets one phase input of the PARK transformation to a constant zero. By means of a proper cancellation, a zero steady state phase angle estimation error can be achieved, even under magnitude and frequency variations. The proposed PLL structure is presented together with guidelines for parameters adjustment. The performance of the proposed PLL is verified by comprehensive experiments. Satisfactory phase angle estimation can be achieved within one input signal cycle, and the estimation error can be totally eliminated in four input cycles for the most severe conditions.

• Journal of Power Electronics
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• v.9 no.1
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• pp.124-131
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• 2009

This paper presents a PWM dc-ac converter regulation using a Single Input Fuzzy PI Controller (SIFPIC). The SIFPIC is derived from the signed distanced method, which is a simplification of a conventional fuzzy controller. The simplification results in a one-dimensional rule table, that allows its control surface to be approximated by a piecewise linear relationship. The controller multi-loop structure is comprised of an outer voltage and an inner current feedback loop. To verify the performance of the SIFPIC, a low power PWM dc-ac converter prototype is constructed and the proposed control algorithm is implemented. The experimental results show that the SIFPIC performance is comparable to a conventional Fuzzy PI controller, but with a much reduced computation time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.