• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.11-20
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• 2014

For Web-based applications in IoT environment, IETF CoRE WG has standardizing the CoAP. One of limitations of CoAP is that CoAP standard does not consider the mobility management of the CoAP sensor node. In this paper, we propose the mobility management protocol of CoAP sensor node by considering the characteristics of the constrained network. The proposed mobility management protocol supports for Web client to be transmitted the sensing data from CoAP node reliably while the CoAP sensor moves into different wireless networks. To do this, we designed the architecture with the separate IP address management of CoAP sensor node and presented the mobility management protocol, which includes the holding and binding mode, in order to provide the reliable transmission. Finally, the numerical analysis and simulation with NS2 tool have been done for the performance evaluation in terms of the handover latency and packet loss with comparing the proposed mobility management protocol with other the existing mobility management protocols. The performance result shows that the proposed mobility management can provide the transmission of sensing data without the packet loss comparing with the existing mobility management protocol reliably.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.73-80
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• 2012

In this article, we propose a P2P-based mobility management protocol for global seamless handover in heterogeneous wireless networks. Unlike previous mobility management protocols such as IETF MIPv4/6 and its variants, the proposed protocol can support global seamless handover without changing the existing network infrastructure. The idea of the proposed protocol is that the location management function for mobility management is separately supported from packet forwarding function, and bidirectional IP tunnels for packet transmission are dynamically constructed between two end-to-end mobile hosts. In addition, early handover techniques have been developed to avoid large handover delays and packet losses using the IEEE 802.21 Media Independent Handover functions. The architecture and signaling procedure of the proposed protocol have been designed in detail, and the mathematical analysis and simulation have been done for performance evaluation. The performance results show that the proposed protocol outperforms the existing MIPv6 and HMIPv6 in terms of handover latency and packet loss.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.6
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• pp.1-11
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• 2000

In this paper, we propose a novel control signaling protocol that efficiently controls connection setup and increases the utilization of network resources. The proposed protocol, Separated Control Signaling Protocol(SCSP), separates bearer control from call control lot WDM optical networks. The main function of call control is to check the availability of network resources such as wavelengths and receivers at destination node. Bearer control is to reserve and assign wavelengths. The signaling architecture of this protocol consists of call controller and hearer controller The call controller handles call setup and release, activates the beater controller, and manages the status of call and bearer. The bearer controller reserves wavelengths, sets up bearer, tears down bearer. and notifies the status of beater to call controller. The state transition diagrams of each controller are designed. Using control messages and related primitives, the information flows for call setup and bearer setup, hearer teardown and call release, and reaction for setup failures are described to evaluate the performance. The simulation results show that the separated control signaling protocol is superior to conventional one in terms of call blocking probability and resource utilization.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.735-741
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• 2016

Increasing the total length of waveguide-below-cutoff array(WBCA) as it is used to the duct in order to enhance shielding effectiveness, the design could cause higher cost, higher levels of difficulties in construction and the interruption a flow velocity. The multi-layered WBCA can compensate for this problem, which can be designed by crossing each waveguide layer. By conducting simulations from 2-layer to 8-layer structure, it can be observed that the shielding effectiveness increases from 52 dB to 75 dB. Comparing with the original WBCA in a shape of mono layer rectangular, our proposed waveguide becomes similar with the original value as the number of crossing layer increases. In addition, the analysis with the flow of fluid in the duct installed multi-layered WBCA are required. We demonstrate this analysis by doing the flow of fluid simulation, and concluded that the multi-layered WBCA has loss of flow of fluid less than unit rectangular WBCA.

• Journal of the Korean Society of Marine Environment & Safety
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• v.22 no.1
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• pp.108-117
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• 2016

In this paper, a portal system compatible with MRV regulation was designed to monitoring, reporting and verifying $CO_2$ emission and fuel consumption data from an international ship. A portal system supports monitoring and reporting task of international shipping companies and calculates national greenhouse gas inventory. EU MRV law, MRV discussions of IMO, responses of international shipping companies to ship energy efficiency and greenhouse gas regulation, and greenhouse gas statistics on international shipping were analyzed to drive portal system requirements. For ship energy efficiency and $CO_2$ emitted monitoring, a data collection module was designed based on on-board equipment, energy efficiency measuring device and navigation report. Data transfer module with easy management and minimized usage to transfer ship data to shore was designed. A portal system was designed to convert the collected data into the standard reporting format, perform monitoring, statical analysis, verification and auto report generation, and support national greenhouse gas inventory.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.12
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• pp.17-27
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• 2011

Most of the previous mobility management protocols such as IETF MIPv4/6 and its variants standardized by the IETF do not support global seamless handover because they require partially changes of the existing network infrastructure. In this article, we propose a simple mobility management protocol (SMMP) which can support global seamless handover between homogeneous or heterogeneous wireless networks. To do this, the SMMP employs separate location management function as DMMS to support global user and service mobility and the bidirectional tunnels are dynamically constructed to support seamless IP mobility by using the IEEE MIH extension server, which is extended the IEEE 802.21 MIH standards. The detailed architecture and functions of the SMMP have been designed. Finally, the mathematical analysis and the simulation have been done. The performance results show the proposed SMMP outperforms the existing MIPv6 and HMIPv6 in terms of handover latency, packet loss, pear signal noise ratio (PSNR).

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.