• Journal of the Korean Association of Geographic Information Studies
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• v.14 no.4
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• pp.128-136
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• 2011

To monitor and predict the change of coastal environment according to the construction of Saemangeum sea dyke and the development of land reclamation, we have done real-time and periodic ocean observation and numerical simulation since 2002. Saemangeum coastal environmental data can be largely classified to marine meteorology, ocean physics and circulation, water quality, marine geology and marine ecosystem and each part of data has been generated continuously and accumulated over about 10 years. The collected coastal environmental data are huge amounts of heterogeneous dataset and have some characteristics of multi-dimension, multivariate and spatio-temporal distribution. Thus the implementation of information system possible to data collection, processing, management and service is necessary. In this study, through the implementation of Saemangeum coastal environmental information system using geographic information system, it enables the integral data collection and management and the data querying and analysis of enormous and high-complexity data through the design of intuitive and effective web user interface and scientific data visualization using statistical graphs and thematic cartography. Furthermore, through the quantitative analysis of trend changed over long-term by the geo-spatial analysis with geo- processing, it's being used as a tool for provide a scientific basis for sustainable development and decision support in Saemangeum coast. Moreover, for the effective web-based information service, multi-level map cache, multi-layer architecture and geospatial database were implemented together.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.55-62
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• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.33-40
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• 2005

This paper describes a design of FFT/IFFT Core(FFT256/2k), which is an essential block in terrestrial DMB modem. It has four operation modes including 256/512/1024/2048-point FFT/IFFT in order to support the Eureka-147 transmission modes. The hybrid architecture, which is composed of R2SDF and R2SDC structure, reduces memory by $62\%$ compared to R2SDC structure, and the SQNR performance is improved by TS_CBFP(Two Step Convergent Block Floating Point). Timing simulation results show that it can operate up to 50MHz(a)2.5-V, resulting that a 2048-point FFT/IFFT can be computed in 41-us. The FFT256/2k core designed in Verilog-HDL has about 68,400 gates and 58,130 RAM. The average power consumption estimated using switching activity is about 113-mW, and the total average SQNR of over 50-dB is achieved. The functionality of the core was fully verified by FPGA implementation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.84-93
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• 2006

Ethernet-PON is an emerging access network technology that provides a low-cost method of deploying optical access lines between OLT and ONUs. It has a point-to-multipoint and multipoint-to-point architecture in downstream and upstream direction, respectively. Therefore, downstream packets are broadcast from an OLT toward all ONUs sithout collision. On the other hand, since alt ONUs share a common channel, the collision may be occurred for the upstream transmission. Therefore, earlier efforts on Ethernet-PON have been concentrated on an upstream MAC protocol to avoid collision. But it is needed to control downstream traffic in practical access network, where the network provider limits available bandwidth according to the number of users. In this paper, we propose a traffic control scheme for supporting the fairness of the downstream bandwidth. The objective of this algorithm is to guarantee the fairness of ONUs while maintaining good performance. In order to do this, we define the service probability that considers the past traffic information for downstream, the number of tokens and the relative size of negotiated bandwidth. We develop the simulation model for Ethernet-PON to evaluate the rate-limiting algorithm by using AWESIM. Some results are evaluated and analyzed in terms of defined fairness factor, delay and dropping rate under various scenario.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of the Korean Society of Environmental Restoration Technology
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• v.22 no.6
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• pp.115-124
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• 2019

In a climate change environment where heat damage and drought occur during a rainy season such as in 2018, a vegetation-based LID system that enables disaster prevention as well as environment improvement is suggested in lieu of an installation-type LID system that is limited to the prevention of floods. However, the quantification of its performance as against construction cost is limited. This study aims to present an experiment environment and evaluation method on quantitative performance, which is required in order to disseminate the vegetation-based LID system. To this end, a 3^rd quartile huff time distribution mass curve was generated for 20-year frequency, 60-minute probable rainfall of 68mm/hr in Cheonan, and effluent was analyzed by recreating artificial rainfall. In order to assess the reliability of the rainfall event simulator, 10 repeat tests were conducted at one-minute intervals for 20 minutes with minimum rainfall intensity of 22.29mm/hr and the maximum rainfall intensity of 140.69mm/hr from the calculated probable rainfall. Effective rainfall as against influent flow was 21.83mm/hr (sd=0.17~1.36, n=20) on average at the minimum rainfall intensity and 142.27mm/hr (sd=1.02~3.25, n=20) on average at the maximum rainfall intensity. In artificial rainfall recreation experiments repeated for three times, the most frequent quartile was found to be the third quartile, which is around 40 minutes after beginning the experiment. The peak flow was observed 70 minutes after beginning the experiment in the experiment zone and after 50 minutes in the control zone. While the control zone recorded the maximum runoff intensity of 2.26mm/min(sd=0.25) 50 minutes after beginning the experiment, the experiment zone recorded the maximum runoff intensity of 0.77mm/min (sd=0.15) 70 minutes after beginning the experiment, which is 20 minutes later than the control zone. Also, the maximum runoff intensity of the experiment zone was 79.6% lower than that of the control zone, which confirmed that vegetation unit-type LID system had rainfall runoff reduction and delay effects. Based on the above findings, the reliability of a lab-level rainfall simulator for monitoring the vegetation-based LID system was reviewed, and maximum runoff intensity reduction and runoff time delay were confirmed. As a result, the study presented a performance evaluation method that can be applied to the pre-design of the vegetation-based LID system for rainfall events on a location before construction.

• Spatial Information Research
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• v.23 no.1
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• pp.1-8
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• 2015

The purpose of this study is to develope BIM Template according to major building material for efficiently and quantitatively evaluating greenhouse gas emission at the design stage. Template users consider various environmental impacts without connecting simulation tools for analyzing environmental impact and Template users who have no prior knowledge can Life Cycle Assessment by using The green template. For this study, Database which was reflected in template was constructed considering environmental performance. and 6 kinds of environmental impact categories and PPS standard construction codes were analyzed by major building material derived from literature. Based on this analyzed data, The major Material Family according to the main building material was developed. When users conduct modeling by utilizing Family established, evaluating result can be confirmed in the Revit BIM Modeling program by using the schedule function of the Revit. Users through the modeling, the decision-making environment performance possible. In addition, we propose to create a guideline for the steps required to build an additional established family.

• The Journal of the Korea Contents Association
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• v.15 no.7
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• pp.1-11
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• 2015

In recent high performance computing system, GPGPU has been widely used to process general-purpose applications as well as graphics applications, since GPU can provide optimized computational resources for massive parallel processing. Unfortunately, GPGPU doesn't exploit computational resources on GPU in executing general-purpose applications fully, because the applications cannot be optimized to GPU architecture. Therefore, we provide GPU research guideline to improve the performance of computing systems using GPGPU. To accomplish this, we analyze the negative factors on GPU performance. In this paper, in order to clearly classify the cause of the negative factors on GPU performance, GPU core status are defined into 5 status: fully active status, partial active status, idle status, memory stall status and GPU core stall status. All status except fully active status cause performance degradation. We evaluate the ratio of each GPU core status depending on the characteristics of benchmarks to find specific reasons which degrade the performance of GPU. According to our simulation results, partial active status, idle status, memory stall status and GPU core stall status are induced by computational resource underutilization problem, low parallelism, high memory requests, and structural hazard, respectively.