• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.128-131
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• 2000

In this paper, the animated simulation system (Anisim) is proposed in order to develope an efficient functional system verification tool. It displays the simulation results of the designed system using graphic animation with various models lot the target system. With simple interface definitions given by the user, Anisim generates interface codes automatically. Users can describe and model the target system with the generated interface codes. Since the simulation engine is implemented in C-language, modeling is very simple and simulation can be performed in real time.

• Journal of the Korea Society for Simulation
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• v.14 no.1
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• pp.19-32
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• 2005

In this study, a distributed simulation of Petri net models under HLA/RTI framework is considered. Throughout our modeling experiences, it is recognized that the proper use of interface specification and time management services are important in order to achieve successful implementation of RTI. The interfacing tokens between Petri net models are distinguished as information entity and physical entity. Both entities are modeled as InteractionClass in order to send and receive messages. For the synchronization of local simulation clocks, a conservative method with NERA service is considered. A cell manufacturing system is modeled and implemented with RTI to illustrate the distributed simulation of Petri net models.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.6
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• pp.1533-1545
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• 1996

In this paper, the design and implementation of echo canceller with new variable step size algorithm is discussed. The method used in the new algorithm is to periodically adopt the test function which helps an optimal coefficient tracking. This algorithm outperforms LMS and VS algorithms in convergence speed and steady state error. As the period of test function is decreased, the speed of convergence is improved, but the number of calculation is increased, then the trade off between these parameters must be considered. Simulation results show new algorithm outperforms LMS and VS algorithms in convergence rate. For the design of hardware, circuit is designed with VHDL, and synthesized with Act1 withc is a FPGA library of ActelTM in use of synovation of InterGraph$^{TM}$. Verification of the synthesized circuit is carried out with simulator DLAB. The circuit based on the algorithm which is suggested in this paper calculated 7 radix places of inary number. A simulation data for the verification is based on the data of algorithm simulation. When the same input data is applied to the both simulation, output results of circuit simulation had slight difference in compare with that of algorithm simulation. The number of used gate is about 5,500 and We have 5.53MHz in maximum frequency.y.

• Journal of the Korean Society of Safety
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• v.14 no.2
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• pp.52-61
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• 1999

This paper proposes the application of fuzzy control for high performance control of induction motor using electric vehicles. A fuzzy controller converts a set of liguistic rules based on expert knowledge into a automatic control strategy. Such controllers have often been found superior to conventional controllers especially when information being processed is inexact and uncertain. A system with fast torque response is very beneficial in applications where direct self control (DSC) is highly desirable. The response of DSC is slower during startup and during change in command torque. Fuzzy control is used for implementation of DSC to improve its slow response. Simulation implementation of the fuzzy logic controller was carried out to verify the behavior of the controller. The simulation results with fuzzy control are compared with those of the conventional DSC. The starting flux and torque response and the responses to the step changes in command torque with fuzzy implementation show a considerable improvement over the conventional control. The steady state responses in both the cases are the same.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.169-170
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• 2012

This paper presents implementation of digital phase controller for thyristor by using FPGA (Field Programmable Gate Array) in HVDC system. Implementation of digital HVDC system is possible by using superior digital simulator such as RTDS (Real Time Digital Simulator). But thyristor phase controller is typically implemented by analog circuit, because it is difficult to implement the phase controller with low operating speed of RTDS. To guarantee high control performance, phase controller needs fast operating speed. This paper presents FPGA based digital phase controller to obtain high speed and high performance. The entire digital simulation of the HVDC system is also implemented by interfacing between FPGA based phase controller and RTDS. Proposed digital HVDC simulator is verified through RTDS simulation.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.560-563
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• 1999

In this paper, we present an optimal hardware implementation for preprocessing of a person identification algorithm utilizing vein pattern of dorsal surface of hand. For the vein pattern recognition, the computational burden of the algorithm lies mainly in the preprocessing of the input images, especially in lowpass filtering. we could reduce the identification time to one tenth by hardware design of the lowpass filter compared to sequential computations. In terms of the computation accuracy, the simulation results show that the CSD code provided an optimized coefficient value with about 91.62% accuracy in comparison with the floating point implementation of current coefficient value of the lowpass filter. The post-simulation of a VHDL model has been performed by using the ModelSim$^{TM}$. The implemented chip operates at 20MHz and has the operational speed of 55.107㎳.㎳.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.3
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.03a
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• pp.78-85
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• 1998

The paper introduces major technical specifications of the Line II railway simulators of Pusan City in Korea. Comparing design specifics of the railway simulators with of the light aircraft Flight Training Device(FTD, the paper reveals commonality of implementation technologies applied to both simulators: Overall configurations and design philosophies are basically the same. In both programs VMEbus computing systems with UNIX are adapted as backbones of the simulators. It is found that the railway simulators are less stringent in real-time requirements than the aircraft FTD, and the railway simulators are designed to be more event-driven and object-oriented. The experiences show that models may be diverse depending on the objects but implementation technologies are about the same. Maximizing portability of implementation technologies is a matter of an organizations strategy of adopting standardized processes and modular technologies available and most economic to them.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.3
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• pp.522-532
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• 2017

In this paper, a new method of SVPWM implementation for 3-Phase 3-Leg 3-Level AC/DC converter known as the Vienna converter is proposed. Also the performances of PI and PR controller used in AC input current controller are compared. To verify the proposed method, PSIM, a power electronics simulation program, is utilized. The performances of the proposed new method and the two existing methods are compared through simulation and experiment. Also PI and PR controller in AC input current controller are compared through 10[kW] Vienna converter system.