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Distributed Arithmetic Adaptive Filter Structure for Low-power Digital Hearing Aid Processor Implementation  

장영범 (상명대 공대 정보통신공학전공)
이원상 (상명대 컴퓨터정보통신공학)
유선국 (연세대 의학공학교실)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers D / v.53, no.9, 2004 , pp. 657-662 More about this Journal
Abstract
The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.
Keywords
Distributed Arithmetic;
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