• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.194-197
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• 2002

Applying dual layer insulator on plastic substrates improved electrical characteristics of organic thin film transistor(TFT). A high-quality silicon dioxide(SiO$_2$) suitable for a insulator was deposited on plastic substrates by e-beam evaporation at 110$^{\circ}C$. The insulator film which was treated by N$_2$ annealing at 150$^{\circ}C$ showed excellent I-V, C-V characteristics. The dual layer insulator structure of polyimide-SiO$_2$ improved the roughness of SiO$_2$ surface and showed very low leakage current. In addition, the flat band voltage has been reduced from -2.5V to about 0.5V.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.409-414
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• 2017

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Korean Journal of Metals and Materials
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• v.46 no.1
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.229-229
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• 2011

부유 게이트 Floating gate (FG) 플래시 메모리 소자의 단점을 개선하기 위해 전하 포획 층에 전하를 저장하는 전하 포획 플래시 메모리 Charge trap flash (CTF)소자에 대한 연구가 활발히 진행되고 있다. CTF소자는 FG플래시 메모리 소자에 비해 비례축소가 용이하고 긴 retention time을 가지며, 낮은 구동 전압을 사용하는 장점을 가지고 있다. CTF 소자에서 비례축소에 따라 단채널 효과와 펀치-쓰루 현상이 증가하는 문제점이 있다.본 연구에서는 CTF 단채널 효과와 펀치-쓰루 현상을 감소시키기 위한 방법으로 silicon-on-insulator (SOI) 기판을 사용하였으며 SOI기판에서 절연층의 깊이에 따른 전기적 특성을 고찰하였다. silicon-oxide-nitride-oxide-silicon(SONOS) 구조를 가진 CTF 메모리 소자를 사용하여 절연층의 깊이 변화에 따른 subthreshold swing특성, 쓰기-지우기 동작 특성을 TCAD 시뮬레이션 툴인 Sentaurus를 사용하여 조사하였다. 소스와 드레인의 junction depth는 20 nm 사용하였고, 절연층의 깊이는 5 nm~25 nm까지 변화하면서 절연층의 깊이가 20 nm이하인 fully depletion 소자에 비해, 절연층의 깊이가 25 nm인 소자는 partially depletion으로 인해서 드레인 전류 레벨이 낮아지고 subthreshold swing값이 증가하는 현상이 나타났다. 절연층의 깊이가 너무 얕을 경우, 채널 형성의 어려움으로 인해 subthreshold swing과 드레인 전류 레벨의 전기적성질이 SOI기판을 사용하지 않았을 경우보다 떨어지는 경향을 보였다. 절연층의 깊이가 17.5 nm인 경우, CTF소자의 subthreshold swing과 드레인 전류 레벨이 가장 좋은 특성을 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.175-177
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• 2002

Electrical characteristics of the Si-O superlattice diode as a function of annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice diode with multilayer Si-O structure showed the stable and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator (SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05b
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• pp.76-81
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• 2004

This paper presents the results of spectral analysis of leakage current waveforms on contaminated insulators under various fog and environment conditions(salt fog, clean fog, rain) The larger the leakage current during 200ms, the higer the power spectrum at 60Hz. For almost equal maximum current during 200ms, however, the spectrum at 60hz and the odd order harmonics increase emphatically when discharges occur continuously for several half-waves. If contaminated insulators suffers from high salt-density fog, the leakage current occurs with high crest value intermittently, results in the low spectrum. Analysis of leakage current data showed that this electrical activity was characterized by transient arcing behavior contaminants are deposited on the insulator surface during salt fog tests. This provides a path for the leakage current to flow along the surface of the insulator. It is important to have an indication of the pollution accumulation in order to evulate the test performance of a particular insulator. If the drop in surface resistivity is severe enough, then the leakage current may escalate into s service interrupting flashover that degrade power quality.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.153-153
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• 2009

We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1449_1450
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• 2009

Surface contamination and leakage current have caused operating problems. A flashover in a substation may result in destruction of an insulator or many others electrical equipment. Engineering plastics have good characteristic (light weight, good productivity and little of void) as compare with epoxy or porcelain insulators. Outdoor insulator must have resistance to contamination. However, they are not suited to outdoor insulator by reason of being not good hydrophobic. RTV has a good property of hydrophobic and ATH has characteristic obstructing exothermic reaction. In order to reduce the incidence of insulator flashover and damage, the silicon rubber contained nano size ATH coat on surface of engineering plastics. In this paper, it compares resistance tracking of the engineering plastic coated RTV with that of non-coated engineering plastic and ATH filled composites performed much better than non-filled composites.