• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.479-483
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• 2017

The effect of $NH_3$ plasma treatment on device characteristics was confirmed for an optimized thin film transistor of poly-Si formed by ELA. When C-V curve was checked for MIS (metal-insulator-silicon), Dit of $NH_3$ plasma treated and MIS was $2.7{\times}10^{10}cm^{-2}eV^{-1}$. Also in the TFT device case, it was decreased to the sub-threshold slope of 0.5 V/decade, 1.9 V of threshold voltage and improved in $26cm^2V^{-1}S^{-1}$ of mobility. Si-N and Si-H bonding reduced dangling bonding to each interface. When gate bias stress was applied, the threshold voltage's shift value of $NH_3$ plasma treated device was 0.58 V for 1,000s, 1.14 V for 3,600s, 1.12 V for 7,200s. As we observe from this quality, electrical stability was also improved and $NH_3$ plasma treatment was considered effective for passivation.

• Journal of Sensor Science and Technology
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• v.21 no.2
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• pp.114-120
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• 2012

This paper describes the design, fabrication and testing of a micromachined resonant accelerometer consisting of a symmetrical pair of proof masses and double-ended tuning fork(DETF) oscillators. Under the external acceleration along the input axis, the proof mass applies forces to the oscillators, which causes a change in their resonant frequency. This frequency change is measured to indicate the applied acceleration. Pivot anchor and leverage mechanisms are adopted in the accelerometer to generate larger force from a proof mass under certain acceleration, which enables increasing its scale factor. Finite element method analyses have been conducted to design the accelerometer and a silicon on insulator(SOI) wafer with a substrate glass wafer was used for fabricating it. The fabricated accelerometer has a scale factor of 188 Hz/g, which is shown to be in agreement with analysis results.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.1
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• pp.89-97
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• 2001

A microgyroscope, which vibrates in two orthogonal axes on the substrate plane, is designed and fabricated. The shuttle mass of the vibrating gyroscope consists of two parts. The one is outer shuttle mass which vibrates in driving mode guided by four folded springs attached to anchors. And the other is inner shuttle mass which vibrates in driving mode as the outer frame does and also can vibrate in sensing mode guided by four folded springs attached to the outer shuttle mass. Due to the directions of vibrating mode, it is possible to fabricate the gyroscope with simplified process by using polysilicon on insulator structure. Fabrication processes of the microgyroscope are composed of anisotropic silicon etching by RIE, gas-phase etching (GPE) of the buried sacrificial oxide layer, metal electrode formation. An eletromechanical model of the vibrating microgyroscope was modeled and bandwidth characteristics of the gyroscope operates at DC 4V and AC 0.1V in a vacuum chamber of 100mtorr. The detection circuit consists of a discrete sense amplifier and a noise canceling circuit. Using the evaluated electromechanical model, an operating condition for high performance of the gyroscope is obtained.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.269-269
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• 2016

최근, 플렉서블 광전자소자 제작 기술의 눈부신 발전으로, 기존의 평면형 이미지 센서가 가지고 있는 여러가지 한계를 극복하기 위해 곡면형 이미지 센서 제작에 대한 다양한 연구가 진행되고 있다. 리소그래피, 물질 성장, 도포, 에칭 등의 대부분의 반도체 공정은 평면 기판에 기반한 공정 방법으로 곡면 구조의 이미지 센서를 제작하기에는 많은 어려움이 있다. 본 연구에서는 곡면형 이미지 센서의 제작을 위해 곡면 구조 위에서의 직접적인 공정 대신 평면 기판에서 단결정 실리콘을 이용해 전사 인쇄가 가능하고 수축이 가능한 초박막 구조의 이미지 센서를 제작한 후 이를 떼어내는 방식을 이용하였다. 이온 주입 및 건식 식각 공정을 통해 평면 SOI (Silicon on Insulator) 기판 위에 단일 광다이오드 배열 형태의 소자를 제작한 후 수 차례의 폴리이미드 층 도포 및 스퍼터링을 통한 금속 배선 공정을 통해 초박막 형태의 광 검출기를 완성한다. 이후 습식 식각 및 폴리디메틸실록산(PDMS) 스탬프를 이용한 전사 인쇄 공정을 통해 기판으로부터 디바이스를 분리하여 변형 가능한 형태의 이미지 센서를 얻을 수 있다. 이러한 박막형 이미지 센서는 유연한 재질로 인해 수축 및 팽창, 구부림과 같은 구조적 변형이 가능하게 되어 겹눈 구조 카메라, 튜너블 카메라 등과 같이 기존 방식의 반도체 공정으로는 구현할 수 없었던 다양한 이미징 시스템 개발에 적용될 수 있을 것으로 기대된다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.29-32
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• 2000

Cerium oxide thin film has been proposed as a buffer layer between the ferroelectric film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS ) structures for ferroelectric random access memory (FRAM) applications. In this study, CeO$_2$thin films were etched with Cl$_2$/Ar gas combination in an inductively coupled plasma (ICP). The highest etch rate of CeO$_2$film is 230 $\AA$/min at Cl$_2$/(Cl$_2$+Ar) gas mixing ratio of 0.2. This result confirms that CeO$_2$thin film is dominantly etched by Ar ions bombardment and is assisted by chemical reaction of Cl radicals. The selectivity of CeO$_2$to YMnO$_3$was 1.83. As a XPS analysis, the surface of etched CeO$_2$thin films was existed in Ce-Cl bond by chemical reaction between Ce and Cl. The results of XPS analysis were confirmed by SIMS analysis. The existence of Ce-Cl bonding was proven at 176.15 (a.m.u.).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.81-82
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• 2006

SOI(Silicon-On-Insulator) MOSFET의 전기적 특성에 미치는 게이트 산화막과 계면준위 밀도의 관계를 조사하였다. 결함이 발생하지 않는 얕은 소스/드레인 접합을 형성하기 위하여 급속열처리를 이용한 고상확산방법으로 제작한 SOI MOSFET 소자는 급속열처리 과정에서 계면준위가 증가하여 소자의 특성이 열화된다. 이를 개선하기 위하여 $H_2/N_2$ 분위기에서 후속 열처리 공정을 함으로써 소자의 특성이 향상됨을 볼 수 있었다. 이와같이 급속열처리 공정과 $H_2/H_2$ 분위기에서의 후속 열처리 공정이 소자 특성에 미치는 영향을 분석하기 위하여 소자 시뮬레이션을 이용하여 게이트 산화막과 채널 사이의 계면준위 밀도를 분석하였다. 그 결과, n-MOSFET의 경우에는 acceptor-type trap, p-MOSFET의 경우에는 donor-type trap density가 소자특성에 큰 영향을 미치는 것을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.17-18
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• 2006

고상 확산 방법을 이용하여 얕은 소스/드레인 접합을 가지는 SOI (Silicon-On-Insulator) MOSFET 소자를 제작하였다. 확산원으로는 PSG(Phosphorus silicate glass) 박막과 PBF(Poly Boron Film) 박막이 각각 n, p-type 소자 형성을 위해 사용되었다. 얕은 접합 형성을 위하여 급속 열처리 방법(RTA: Rapid Thermal Annealing)을 이용하여 PSG와 PBF로부터 인과 붕소를 SOI MOSFET 소자의 소스/드레인으로 확산시켰다. 또한, 소자 특성 개선을 위한 후 속 열처리 공정으로 희석된 수소 분위기 중에서 FA(Furnace Annealing)를 실시하였다. SPD 기술을 적용하여 10 nm 이하의 매우 얕은 p-n 접합을 형성할 수 있었고, 양호한 다이오드 특성을 얻을 수 있었다. 또한, SPD 방법으로 결함이 없는 접합 형성이 가능하며, 소자 제작 공정의 최적화를 통해 차세대 CMOS 소자로 기대되는 SOI MOSFET를 성공적으로 제작할 수 있었다.

• Progress in Superconductivity
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• v.12 no.2
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• pp.114-117
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• 2011

We report our efforts on the development of Nb-based non-hysteretic Josephson junction fabrication process for quantu device applications. By adopting and modifying the existing Nb-aluminum oxide tunnel junction process, we develop a process for non-hysteretic Josephson junction circuits using metal-silicide as metallic barrier material. We use sputter deposition of Nb and $MoSi_2$, PECVD deposition of silicon oxide as insulator material, and ICP-RIE for metal and oxide etch. The advantage of the metal-silicide barrier in the Nb junction process is that it can be etched in $SF_6$ RIE together with Nb electrode. In order to define a junction area precisely and uniformly, end-point detection for the RIE process is critical. In this paper, we employed thin Al layer for the etch stop, and optimized the etch condition. We have successfully demonstrated that the etch stop properties of the inserted Al layer give a uniform etch profile and a precise thickness control of the base electrode in Nb trilayer junctions.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.1 no.1
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• pp.87-94
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• 2001

Silicon nitride films grown by plasma-enhanced chemical vapor deposition (PECVD) are useful for a variety of applications, including anti-reflecting coatings in solar cells, passivation layers, dielectric layers in metal/insulator structures, and diffusion masks. PECVD systems are controlled by many operating variables, including RF power, pressure, gas flow rate, reactant composition, and substrate temperature. The wide variety of processing conditions, as well as the complex nature of particle dynamics within a plasma, makes tailoring SiN film properties very challenging, since it is difficult to determine the exact relationship between desired film properties and controllable deposition conditions. In this study, SiN PECVD modeling using optimized neural networks has been investigated. The deposition of SiN was characterized via a central composite experimental design, and data from this experiment was used to train and optimize feed-forward neural networks using the back-propagation algorithm. From these neural process models, the effect of deposition conditions on film properties has been studied. A recipe synthesis (optimization) procedure was then performed using the optimized neural network models to generate the necessary deposition conditions to obtain several novel film qualities including high charge density and long lifetime. This optimization procedure utilized genetic algorithms, hybrid combinations of genetic algorithm and Powells algorithm, and hybrid combinations of genetic algorithm and simplex algorithm. Recipes predicted by these techniques were verified by experiment, and the performance of each optimization method are compared. It was found that the hybrid combinations of genetic algorithm and simplex algorithm generated recipes produced films of superior quality.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.309-313
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• 2006

We demonstrated 2.2inch qqVGA AMOLED display drived by ultra low temperature poly-Si (ULTPS) TFT not transferred but direct fabricated below $200^{\circ}C$. Si channel was crystallized by decreasing impurity concentration even at room temperature. Gate insulator with a breakdown field exceeding 8 MV/cm was realized by Inductively coupled plasma - CVD. In order to reduce stress of plastic, organic film was coated as inter-dielectric and passivation layers. Finally, ULTPS TFT of which mobility is over $20cm^2/Vsec$ was fabricated on transparent plastic substrate and drived OLED display successfully.