• ETRI Journal
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• v.38 no.1
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• JOURNAL OF ELECTRICAL WORLD
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• s.297
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• pp.66-72
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• 2001

1957년에 사이리스터가 발표된 이래 파워반도체디바이스(이하 ''파워디바이스''라 한다)의 발전과 더불어 이것을 사용하여 전력변환$\cdot$제어와 이를 응용한 파워일렉트로닉스 산업도 현저한 발전을 이루어 왔다. 21세기를 맞이하여 지구의 유한성을 강하게 인식하고 자원과 에너지를 고도이용하는 순환형 사회에로의 전환을 도모하는 기술혁신과 IT(정보기술)를 구사한 기술보급의 움직임이 활발해지고, 파워일렉트로닉스와 그 키파트인 파워디바이스가 수행하여야 할 역할은 점점 더 중요해지고 있다. 이와 같은 배경 하에서 파워디바이스는 인버터제어를 주목적으로 사이리스터, GTO(Gate Turn-off Thyristor), 바이폴라트랜지스터, MOSFET(Metal Oxide Silicon Field Effect Transistor)에서 IGBT(Insulated Gate Bipolar Transistor)에로 진전되고, 그 응용분야도 가전제품에서 OA, 산업, 의료, 전기자동차, 전철, 전력에 이르는 폭넓은 분야로 확대되었다. 현재 파워디바이스를 취급하는 전력의 범위는 수W의 스위칭 전원에서 GW급의 직류송전까지 9단위까지에 이르러 광범위한 전력 제어가 가능하게 되었다. 한편 응용의 중심이 되는 IGBT는, 고속화와 저손실화 및 파괴 내량의 향상을 지향한 개량을 거듭하여 제5세대제품이 나타나기 시작하였다. 또한 IGBT에 구동$\cdot$보호$\cdot$진단 회로 등을 넣어 모듈화한 IPM(Intelligent Power Module)이 그 편리성과 소형화를 특징으로 파워디바이스의 주역의 자리에 정착하였다. 가전$\cdot$산업$\cdot$자동차$\cdot$전철의 각 분야에서는 시장 니즈에 최적 설계된 IPM이 개발되게 되어 보다 더한 시장확대가 기대되고 있다. 또한 종래의 Si(실리콘)에 대신하는 반도체 재료로서 SiC(실리콘 카바이드 : 탄화규소)에 대한 기대가 크고 MOSFET나 SBD 등의 파워디바이스의 조기실용화에의 대처노력도 주목할 만하다.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.104-104
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• 1999

Cerium dioxide 박막의 포토루미네슨에 관해서는 Cerium 4f band에서 oxygen 2p band로의 transition에 의한 발광(400nm) 현상이 보고되었다. 또한 Indium Oxide 박막의 발광(637nm0 현상이 보고되었다. 본 연구에서는 3족인 Indium을 Si/In/CeO2/Si 구조와 CeO2/Si 구조에 도핑하여 포토루미네슨스 현상을 관찰하였다. E-beam evaporator를 사용하여 Silicon(111) 기판에 Cerium dioxcide 박막을 성장시킨 경우의 두가지 시료를 분석하였다. 포토루미네슨스 관찰을 위해서 Ge-Cd laser (325nm)가 사용되었으며 Indium의 도핑양과 분포 상태를 알기 위해 SIMS와 ADP를 이용하여 분석하였다. Indium양에 대한 포토루미네슨스 변화와 열처리 후의 indium의 분포의 변화에 의한 포토루미네슨스 변화를 관찰하였다. 상온에서 In/CeO2/Si 시료와 Si/In/CeO2/Si 시료에 대한 포토루미네슨스 현상을 관찰한 결과 Si/In/CeO2/Si 시료에서만 500nm(2.5eV)에서 발광 현상이 관찰되었다. 도핑된 indium은 ADP에서는 검출되지 않고 SIMS에서만 검출되어 ADP의 detection range(1-0.1%) 이하의 양이 도핑된 것으로 추측된다. 도핑된 Indium의 양이 증가할수록 포토루미네슨스의 Intensity가 증가하였다. 또한 열처리(110$0^{\circ}C$, 1min) 후 포토루미네슨스의 peak위치가 390nm(3.18eV)로 변화하였다. Si/In/CeO2/Si에서 포토루미네슨스 현상이 관측되고 Intensity가 indium의 양에 의존하므로 완전하지 못한 Cerium dioxide의 CeOx 구조와 indium과의 결합이 포토루미네슨스의 원인으로 추측된다. 열처리 후 SIMS의 분석결과 indium의 분포가 변화하였으며 이는 포토루미네슨스의 변화의 원인으로 판단된다.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1314-1319
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• 2017

A handheld sheet resistance meter that can easily and quickly measure the sheet resistance of indium tin oxide films was developed. The dual-configuration four-point probe method was adopted for this instrument, which measured sheet resistance in the range from $0.26{\Omega}/sq$. to $2.6k{\Omega}/sq$. with 0.3 % ~ 0.5 % uncertainty. The screen of the instrument displayed the sheet resistance when the probe was in contact with the sample surface and the value continued to be displayed during the probe contact. Even after separating the probe from the surface, the value was still displayed on the screen and could be read easily. A feature of the instrument was the use of the dual-configuration technique to reduce edge effects markedly compared with the single-configuration technique and its ease of operation without applying correction factors for sample size and thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.29-32
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• 2000

Cerium oxide thin film has been proposed as a buffer layer between the ferroelectric film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS ) structures for ferroelectric random access memory (FRAM) applications. In this study, CeO$_2$ thin films were etched with Cl$_2$/Ar gas combination in an inductively coupled plasma (ICP). The highest etch rate of CeO$_2$ film is 230 $\AA$/min at Cl$_2$/(Cl$_2$+Ar) gas mixing ratio of 0.2. This result confirms that CeO$_2$ thin film is dominantly etched by Ar ions bombardment and is assisted by chemical reaction of Cl radicals. The selectivity of CeO$_2$ to YMnO$_3$ was 1.83. As a XPS analysis, the surface of etched CeO$_2$ thin films was existed in Ce-Cl bond by chemical reaction between Ce and Cl. The results of XPS analysis were confirmed by SIMS analysis. The existence of Ce-Cl bonding was proven at 176.15 (a.m.u.).

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.18-19
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• 2017

This paper shows the design of the high voltage capacitor charger which using a modified series parallel resonant converter. The used silicon carbide Metal-Oxide Semiconductor Field Effect Transistor (SiC MOSFET) is proper for the few hundred kHz of high switching frequency to overcome the bulk resonant inductor and snubber capacitors. Furthermore, to increase the amount of the charging current, three phase delta transformer is used as well as the secondary sides are connected in parallel. In this paper, the design procedure of the high voltage capacitor charger is suggested and the output power is verified by the experimental results with the rated resistor load.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.149-153
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• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.82-85
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• 1992

In this study, charge pumping method was used to investigate the Si-SiO$_2$interface characteristics of the nonvolatile SNOSFET memory devices, fabricated using the CMOS 1 Mbit processes (1.2$\mu\textrm{m}$ design rule), with thin oxide layer of 30${\AA}$ thick and nitride layer of 525${\AA}$ thick on the n-type silicon substrate (p-channel). Charge pumping current characteristics with the pulse base level were measured for various frequencies, falling times and rising times. By means of the charge dynamics in a non-steady state, the average Si-SiO$_2$interface state density and capture cross section were determined to be 3.565${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ and 4.834${\times}$10$\^$-16/$\textrm{cm}^2$, respectively. However Si-SiO$_2$ interface state densities were disributed 2.8${\times}$10$\^$-11/～5.6${\times}$10$\^$11/cm$\^$-2/～6${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ in the lover half of energy gap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.327-327
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• 2007

This paper reports the simulation results of piezoelectric microspeakers due to structural changes(diaphragm materials, corrugation width and electrode shapes). When we compared the dependence of diaphragm material properties, the microspeaker with LTO(Low Temperature Oxide) diaphragm shows higher deflection than that of silicon nitride diaphragm, even though the resonant frequencies are almost same in both cases. In case of circular-electrode microspeaker, the deflection of diaphragm is about $16\;{\mu}m$ at 20 V, and it decreases as the corrugation width is decreased. However, the deflection of diaphragm with the square-electrode reveals almost twice times higher value at the same applied voltage than the circular one, and it increases as the corrugation depths are decreased from $30\;{\mu}m\;to\;10\;{\mu}m$. The first resonant frequency of microspeakers present about 1.8 kHz in circular-electrode and 1.2 kHz in square-electrode, respectively.