• 전기전자학회논문지
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• 제7권2호
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• pp.245-252
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• 2003

디지털 보정 기능을 갖는 CMOS 압력 센서의 인터페이스 회로를 설계하였다. 인터페이스 회로는 아날로그 부분과 디지털 부분으로 구성되어 있다. 아날로그 부분은 센서로부터 발생한 약한 신호를 증폭시키는 역할을 담당하고 디지털 부분은 온도 보상 및 오프셋 보정 기능을 담당하며 센서 칩과 보정을 조정하는 마이크로컨트롤러와의 통신을 담당한다. 디지털 부분은 I2C 직렬 인터페이스, 메모리, 트리밍 레지스터 및 제어기로 구성된다. I2C 직렬 인터페이스는 IO 핀 수 및 실리콘 면적 면에서 실리콘 마이크로 센서의 요구에 맞게 최적화 되었다. 이 설계의 주요 부분은 최적화된 I2C 프로토콜을 구현하는 제어 회로를 설계하는 것이다. 설계된 칩은 IDEC의 MPW를 통하여 제작되었다. 칩의 테스트를 위하여 테스트 보드를 제작하였으며 테스트 결과 예상한대로 디지털 보정기능이 잘 수행됨을 확인하였다.

• ETRI Journal
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• 제27권5호
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• 한국공작기계학회논문집
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• 제16권5호
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• pp.134-139
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• 2007

This paper presents a computer-based analysis on the thermal shock characteristics of Pb-free solder joints and UBM in flip chip assemblies. Among four types of popular UBM systems, TiW/Cu system with 95.5Sn-3.9Ag-0.6Cu solder joints was chosen for simulation. A simple 3D finite element model was first created only including silicon die, mixture between underfill and solder joints, and substrate. The displacements due to CTE mismatch between silicon die and substrate was then obtained through FE analysis. Finally, the obtained displacements were applied as mechanical loads to the whole 2D FE model and the characteristics of flip chip assemblies were analyzed. In addition, based on the hyperbolic sine law, the accumulated creep strain of Pb-free solder joints was calculated to predict the fatigue life of flip chip assemblies under thermal shock environments. The proposed method for fatigue life prediction will be evaluated through the cross check of the test results in the future work.

• ETRI Journal
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• 제40권6호
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• pp.759-773
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• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

• ETRI Journal
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• 제36권4호
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• 한국화재소방학회논문지
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• 제10권2호
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• International Journal of Internet, Broadcasting and Communication
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• 제7권2호
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.467-468
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• 2012

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.99.3-99
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• 1998

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.51-51
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• 2012

There is a growing interest in innovative chemical synthesis in microreactors owing to high efficiency, selectivity, and yield. In microfluidic systems, the low-volume spatial and temporal control of reactants and products offers a novel method for chemical manipulation and product generation. Glass, silicon, poly(dimethylsiloxane) (PDMS), and plastics have been used for the fabrication of miniaturized devices. However, these materials are not the best due to either of low chemical durability or expensive fabrication costs. In our group, we have recently addressed the demand for economical resistant materials that can be used for easy fabrication of microfluidic systems with reliable durability. We have suggested the use of various specialty polymers such as silicon-based inorganic polymers and fluoropolymer, flexible polyimide (PI) films that have not been used for microfluidic devices, although they have been used for other areas. And inexpensive lithography techniques were used to fabricate Lab-on-a-Chip type of microreactors with differently devised microchannel design. These microreactors were demonstrated for various synthetic reactions: liquid, liquid-gas organic chemical reactions in heterogeneous catalytic processes, syntheses of polymer and non-trivial inorganic materials. The microreactors were inert, and withstand even harsh conditions, including hydrothermal reaction. In addition, various built-in microstructures inside the microchannels, for example Pd decorated peptide nanowires, definitely enhance the uniqueness and performance of microreactors. These user-friendly Lab-on-a-Chip devices are useful alternatives for chemist and chemical engineer to conventional chemical tools such as glass.