• Journal of the Microelectronics and Packaging Society
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• v.9 no.2
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• pp.49-54
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• 2002

Cobalt silcides thin films were prepared on Poly-Si/$SiO_2$/Si substrates by Co metal depostion using E-beam evaporation method and rapid thermal annealing for the application of inkjet printing heater. The crystal phases and composition distributions of the films were investigated as functions of the rapid thermal annealing (RTA) temperatures (600~$900^{\circ}C$) and times (20~40 sec). The high temparature thermal stability was also investigated by the analysis of sheet resistance and crystalline properties. The stable $CoSi_2$ phases were obtained by the RTA annealing at $800^{\circ}C$ for 20 seconds showing $0.8 \Omega /\Box$ of sheet resitance. However, the sheet resistances were sharply increased at below $700^{\circ}C$ due to changes of crystalline phases. The temperature resistance coefficient of heating elements was found to be about $0.0014/^{\circ}C$, and the obtained cobalt silicided films can be applied to the printer heating elements.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.29-33
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• 2003

Material and electrical properties of copper-based ohmic contacts on n-type 4H-SiC were investigated for the effects of the post-annealing and the metal covering conditions. The ohmic contacts were prepared by sequential sputtering of Cu and Si layers on SiC substrate. The post-annealing treatment was performed using RTP (rapid thermal process) in vacuum and reduction ambient. The specific contact resistivity ($p_{c}$), sheet resistance ($R_{s}$), contact resistance ($R_{c}$), transfer length ($L_{T}$), were calculated from resistance (RT) versus contact spacing (d) measurements obtained from TLM (transmission line method) structure. The best result of the specific contact resistivity was obtained for the sample annealed in the reduction ambient as $p_{c}= 1.0 \times 10^{-6}\Omega \textrm{cm}^2$. The material properties of the copper contacts were also examined by using XRD. The results showed that copper silicide was formed on SiC as a result of intermixing Cu and Si layer.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.439-445
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• 2007

SiGe integrated circuits are being used in the field of high-speed wire/wireless communications and microwave systems due to the RF/high-speed analog characteristics and the easiness in the fabrication. Reducing the resistance variation in SiGe thin film resistors results in enhancing the reliability of integrated circuits. In this paper, we investigate the causes that generate the resistance nonuniformity after the silicon-based thin film resistor was fabricated, and consider the counter plan against that. Because the Ti-B precipitate, which formed during the silicide process of the SiGe thin film resistor, gives rise to the nonuniformity of SiGe resistors, the boron ions should be implanted as many as possible. In addition, the resistance deviation increases as the size of the contact hole that interconnects the SiGe resistor and the metal line decreases. Therefore, the size of the contact hole must be enlarged in order to reduce the resistance deviation.

• Korean Journal of Materials Research
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• v.13 no.5
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• pp.279-284
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• 2003

The $CoSi_2$ process is widely employed in a salicide as well as an ohmic layer process. In this experiment, we investigated the characteristics of $CoSi_2$ films by combinations of I-type (TiN 100$\AA$/Co 150$\AA$), II-type(TiN 100$\AA$/Co 150$\AA$/Ti 50$\AA$), III-type(Ti 100$\AA$/Co 150$\AA$/Ti 50$\AA$), and IV-type(Ti 100$\AA$/Co 150$\AA$/Ti 100$\AA$). Sheet resistances of $CoSi_2$ show the lowest resistance with 2.9 $\Omega$/sq. in a TiN/Co condition and much higher resistances in conditions simultaneously applying Ti capping layers and Ti interlayers. Though we couldn't observe a $CoSi_2$roughness dependence on the film stacks from RMS values, Ti capping layers turned into 78∼94$\AA$ thick TiN layers of (200) preferred orientation at $N_2$ambient. In addition, Ti interlayers helped to form the epitaxial $CoSi_2$with (200) preferred orientation and ternary compounds of Co-Ti-Si. We propose that film structures of II-type and III-type may be appropriate in the salicide process and the ohmic layer process from the viewpoint of Co diffusion kinetics and the CoSi$_2$epitaxy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.173-176
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• 2004

In this study we investigated post ELA(Excimer Laser Annealing) effect on SMC (Silicide Mediated Crystalization) poly-Si (Polycrystalline Silicon) to improve the characteristics of poly-Si. Combining SMC and XeCl ELA were used to crystallize the a-Si (amorphous Silicon) at various ELA energy density for LTPS (Low Temperature Polycrystalline Silicon). We fabricated the conventional SMC poly-Si with no SPC (Solid Phase Crystallization) phase using UV heating method[1] and irradiated excimer laser on SMC poly-Si, so called SMC-ELA poly-Si. After using post ELA we can get better surface morphology than conventional ELA poly-Si and enhance characteristics of SMC poly-Si. We also observed the threshold energy density regime in SMC-ELA poly-Si like conventional ELA poly-Si.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.177-184
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• 2014

In chemical vapor deposition(CVD) tungsten silicide(WSix) dual poly gate(DPG) scheme, we observed the fluorine effects on gate oxide using the electrical and physical measurements. It is found that in fluorine-rich WSix NMOS transistors, the gate thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In PMOS transistors, it is observed that boron of background dopoing in $p^+$ poly retards fluorine diffusion into the gate oxide. Thus, it is suppressed the fluorine effects on gate oxide thickness with the channel length dependency.

• Korean Journal of Materials Research
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• v.27 no.2
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• pp.94-99
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• 2017

Dinickel-silicide $(Ni_2Si)/glass$ was employed as a counter electrode for a dye-sensitized solar cell (DSSC) device. $Ni_2Si$ was formed by rapid thermal annealing (RTA) at $700^{\circ}C$ for 15 seconds of a 50 nm-Ni/50 nm-Si/glass structure. For comparison, $Ni_2Si$ on quartz was also prepared through conventional electric furnace annealing (CEA) at $800^{\circ}C$ for 30 minutes. XRD, XPS, and EDS line scanning of TEM were used to confirm the formation of $Ni_2Si$. TEM and CV were employed to confirm the microstructure and catalytic activity. Photovoltaic properties were examined using a solar simulator and potentiostat. XRD, XPS, and EDS line scanning results showed that both CEA and RTA successfully led to tne formation of nano $thick-Ni_2Si$ phase. The catalytic activity of $CEA-Ni_2Si$ and $RTA-Ni_2Si$ with respect to Pt were 68 % and 56 %. Energy conversion efficiencies (ECEs) of DSSCs with $CEA-Ni_2Si$ and $RTA-Ni_2Si$catalysts were 3.66 % and 3.16 %, respectively. Our results imply that nano-thick $Ni_2Si$ may be used to replace Pt as a reduction catalytic layer for a DSSCs. Moreover, we show that nano-thick $Ni_2Si$ can be made available on a low-cost glass substrate via the RTA process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.73-80
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• 1990

The formation of Ti-silicides with the type of substrate, the species and the concentration of dopant, and the annealing temperature was investigated with sheet resistance and thickness measurement, elemental depth profilling, and microstructure. It was directly affected by the type of substrate, the species and the concentration of dopant, and the annealing temperature. For the amorphous Si substrate, the smothness of $TiSi_2/Si$ interface was increased. Above concentr-ation of $1{\times}10^{16}ions/cm^2$, the rate of $TiSi_2/Si$ formation was decreased and the sheet resistance was increased. The initial profile of dopant according to the implantation energy was one of the factors influencing the out-diffusion of dopant. In $POCI_3$ process, this was less than in ion implantation process.

• Proceedings of the Korea Crystallographic Association Conference
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• 2002.11a
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• pp.42-43
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• 2002

반도체 디바이스의 발전은 높은 직접화 및 동작 속도를 추구하고 있으며, 이를 위해서 MOSFET의 scale down시 발생되는 문제를 해결해야만 한다. 특히, Channel이 짧아짐으로써 발생하는 device의 열화현상으로 동작전압의 조절이 어려워 짐을 해결해야만 하며, gate oxide 두께를 줄임으로써 억제할 수 있다고 알려져 왔다. 현재, gate oxide으로 사용되고 있는 SiO2박막은 비정질로써 ～8.7 eV의 높은 band gap과 Si기판 위에서 성장이 용이하며 안정하다는 장점이 있으나, 두께가 1.6 nm 이하로 얇아질 경우 전자의 direct Tunneling에 의한 leakage current 증가와 gate impurity인 Boron의 channel로의 확산, 그리고 poly Si gate의 depletion effect[1,2] 등의 문제점으로 더 이상 사용할 수 없게 된다. 2001년 ITRS에 의하면 ASIC제품의 경우 2004년부터 0.9～l.4 nm 이하의 EOT가 요구된다고 발표하였다. 따라서, gate oxide의 물리적인 두께를 증가시켜 전자의 Tunneling을 억제하는 동시에 유전막에 걸리는 capacitance를 크게 할 수 있다는 측면에서 high-k 재료를 적용하기 위한 연구가 진행되고 있다[3]. High-k 재료로 가능성 있는 절연체들로는 A1₂O₃, Y₂O₃, CeO₂, Ta₂O, TiO₂, HfO₂, ZrO₂,STO 그리고 BST등이 있으며, 이들 재료 중 gate oxide에 적용하기 위해 크게 두 가지 측면에서 고려해야 하는데, 첫째, Si과 열역학적으로 안정하여 후속 열처리 공정에서 계면층 형성을 배제하여야 하며 둘째, 일반적으로 high-k 재료들은 유전상수에 반비례하는 band gap을 갖는 것으로 알려줘 있는데 이 Barrier Height에 지수적으로 의존하는 leakage current때문에 절연체의 band gap이 낮아서는 안 된다는 점이다. 최근 20이상의 유전상수와 ～5 eV 이상의 Band Gap을 가지며 Si기판과 열역학적으로 안정한 ZrO₂[4], HfiO₂[5]가 관심을 끌고 있다. HfO₂은 ～30의 고유전상수, ～5.7 eV의 높은 band gap, 실리콘 기판과의 열역학적 안전성 그리고 poly-Si와 호환성등의 장점으로 최근 많이 연구가 진행되고 있다. 또한, Hf은 SiO₂를 환원시켜 HfO₂가 될 수 있으며, 다른 silicide와 다르게 Hf silicide는 쉽게 산화될 수 있는 점이 보고되고 있다.

• Current Photovoltaic Research
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• v.1 no.1
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• pp.63-68
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• 2013

We investigated the effects of Au eutectic reaction on Si thin film growth by hot wire chemical vapor deposition. Small SiC and Si nano-particles fabricated through a wet etching process were coated and biased at 50 V on micro-textured Si p-n junction solar cells. Au thin film of 10 nm and a Si thin film of 100 nm were then deposited by an electron beam evaporator and hot wire chemical vapor deposition, respectively. The Si and SiC nano-particles and the Au thin film were structurally embedded in Si thin films. However, the Au thin film grew and eventually protruded from the Si thin film in the form of Au silicide nano-balls. This is attributed to the low eutectic bonding temperature ($363^{\circ}C$) of Au with Si, and the process was performed with a substrate that was pre-heated at a temperature of $450^{\circ}C$ during HWCVD. The nano-balls and structures showed various formations depending on the deposited metals and Si surface. Furthermore, the samples of Au nano-balls showed low reflectance due to surface plasmon and quantum confinement effects in a spectra range of short wavelength spectra range.