• Journal of Sensor Science and Technology
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• v.16 no.5
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• pp.342-348
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• 2007

A high-speed signal processor for Fabry-Perot interferometric sensors using modified ramp modulation is implemented. The main idea for the signal processing is to find a modulation waveform that could induce a linear frequency change in a laser diode to linearize the relationship between the optical phase shift and measurand. It is found that the waveform could be modeled as the addition of a linear term and an exponential term. A signal processor adopting modified ramp modulation technique is implemented and evaluated to find linearity, drift and random walk of $<{\pm}1.5%$, $0.4^{\circ}C$, $5.28{\times}10^{-4}^{\circ}C/{\sqrt{Hz}}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.890-893
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• 2014

In this paper, we present a signal processing algorithm for a marine radar system, in which the evaluation of probability of collision as well as target detection and tracking are performed. Moreover, the digital signal processor that implements the algorithm is proposed. As simulation environment, a mechanically scanning antenna utilizing FMCW signal is used, conducting the beamforming operation with 1 degrees intervals. Test board consists of DSP chips and FPGA, which enable the implemented system to operate in real-time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1217-1220
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• 2005

In this paper, statistical simulation is applied to a superscalar digital signal processor architecture using DSP kernel and DSP application benchmarks. As a result, the performance of a digital signal processor with several microarchitecture configurations can be estimated with the relative error of 3.7 ${\backslash}%$ on the average.

• Proceedings of the Acoustical Society of Korea Conference
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• 1984.12a
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• pp.63-65
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• 1984

In this paper, the implementation of the real time LPC synthesizer using NEC 77p20, the DSP (Digital Signal Processor) chip which facilitates and simplifies the digital hardware, is considered. This method shows the good quality with the low bit rate below 9.6kbps and has the advantage of the flexibility and the simplicity.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.207-208
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• 2006

기존의 음향측심기는 복잡한 하드웨어 구조로 인해 크기와 중량이 큰 단점이 있었다. 이에 본 개발에서는 이러한 단점을 보완하기 위해 고속의 단일칩을 적용하여 단순구조의 하드웨어로 구성하였으며, 그 결과 장비의 크기 및 중량을 감소시킬 수 있었고 또 신호처리 기법을 적용하여 측정 데이터의 안정성을 획득 하였다.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1178-1183
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• 1990

A digital signal processor(DSP) is applied to realizing a compensator of control system of active magnetic bearings, to restrict a resonance caused by the first-order bending vibration of a flexible rotor, and to run the rotor beyond the critical speed. A full-order observer is applied to the translatory rotor-motion with the first-order vibration mode. A PID control is used for the conical motion. The rotor used in the experiments is symmetric, and an electromagnet and a displacement sensor are set in collocation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.10
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• pp.863-871
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• 2017

LMS (least mean square) algorithm widely used in the AVCS (active vibration control system) of helicopters calculates control input using the forward path transfer function and error signal. If the error signal is sinusoidal, it can be represented as the combination of cosine and sine functions with frequency and phase synchronized with the reference signal. The control input also has the same frequency, therefore control algorithm can be simply implemented if the cosine and the sine amplitudes of the control input are calculated and the frequency and phase of the reference signal are used. Calculation of the control input is implemented as simple matrix operation and the change of the control command is slower than the frequency of the error signal, consequently control algorithm can be operated at lower frequency. The signal processing algorithm extracting cosine and sine components of the error signals are modeled using Simulink and PIL (processor-in-the-loop) mode simulation was executed for real-time performance evaluation.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.85-91
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• 2020

Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.4
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• pp.347-354
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• 2022

The synthetic aperture radar(SAR) is an equipment that can acquire images in all weathers day and night based on radar signals. The on-board processor of satellite SAR generates transmission signal by digital signal processing, converts it into an analog signal and transmits to antenna. Until the transmission signal generated by on-board processor is output, the signal passes the transmission cables and analog devices. At this time, these hardware distort the signal and makes SAR performance worse. To improve the performance, pre-distortion technique is used. But, general pre-distortion using taylor series is not sufficient to compensate for the distortion. This paper suggests transmit signal design method with improved pre-distortion. This paper uses envelop sampling method and interpolation filter for frequency domain compensation. The proposed method accurately compensates the hardware distortion and reduces resource usage of FPGA. To analyze proposed method's performance, IRF characteristics are compared when the proposed method applies to signal with errors.