• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.882-885
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• 2003

In this paper, nonlinear echo cancellation using a correlation LMS (CLMS) algorithm is proposed to cancel the undesired nonlinear echo signals generated in the hybrid system of the telephone network. In the telephone network, the echo signals may result the degradation of the network performance. Furthermore, digital to analog converter (DAC) and analog to digital converter (ADC) may be the source of the nonlinear distortion in the hybrid system. The adaptive filtering technique based on the nonlinear Volterra filter has been the general technique to cancel such a nonlinear echo signals in the telephone network. But in the presence of the double-talk situation, the error signal for tap adaptations will be greatly larger, and the near-end signal can cause any fluctuation of tap coefficients, and they may diverge greatly. To solve a such problem, the correlation LMS (CLMS) algorithm can be applied as the nonlinear adaptive echo cancellation algorithm. The CLMS algorithm utilizes the fact that the far-end signal is not correlated with a near-end signal. Accordingly, the residual error for the tap adaptation is relatively small, when compared to that of the conventional normalized LMS algorithm. To demonstrate the performance of the proposed algorithm, the DAC of hybrid system of the telephone network is considered. The simulation results show that the proposed algorithm can cancel the nonlinear echo signals effectively and show robustness under the double-talk situations.

• 융합신호처리학회논문지
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• 제3권4호
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• pp.23-28
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• 2002

본 논문에서는 그레이 레벨 영상을 세선화 하는 과정에서 골격이 끊어지는 것을 방지하는 연결성 복구 알고리즘을 구현하는 하드웨어 구조를 제안하였다. 영상에서 물체의 골격선을 찾아내는 영상의 세선화 과정을 실시간으로 처리하기 위해서는 실시간으로 골격선의 연결성을 검사하는 하드웨어가 필요하다. 본 논문에서는 골격선의 연결성을 4-클럭에 구하는 하드웨어 구조를 제안하였다. 제안된 구조는 PS(Parallel to Serial) Converter 블록, State Generator 블록, Ridge Checker 블록이 연속적으로 연결되어 있다. PS Converter 블록에서는 3$\times$3 그레이 레벨 영상을 4개의 직렬 화소값으로 만들어 State Generator 블록으로 보낸다. Staかe Generator 블록에서는 3$\times$3 그레이 값의 가운데 화소가 골격선에 접하는지를 검사하고, Ridge Checker 블록에서는 가운데 화소가 골격선상에 있는지를 판단한다. 본 논문에서 제안하는 구조는 3$\times$3 그레이 레벨의 가운데 화소의 연결성을 4-클럭에 검사한다. 전체적인 회로는 설계 툴을 사용하여 검증하였고 정상적인 동작을 수행하였다.

• 한국광학회지
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• 제16권4호
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• pp.392-396
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• 2005

본 논문에서는 파장 분할 다중화 방식 광통신에의 적용을 목적으로 하는 다채널 가변형 파장 변환기(Wavelnength Convertor)를 구성하여 이의 성능을 분석하였다. 파장 변환기는 반도체 광증폭기(SOA : Semiconductor Optical Amplifier)의 상호 이득 변조(XGM : Cross Gain Modulation) 특성을 이용한 파장 변환 방식이 이용되었다. 2.5 Gbps 광통신 기반 100 CHz의 채널 간격을 갖는 다채널 신호들에 대한 파장 변환 성능을 측정, 분석하였다. 본 파장 변환기의 상호 이득 변조 성능을 측정한 결과, 소광비(Extinction Ratio)와 비트 오류율(BER : Bit Error Rate) 등의 검증에서 2.5 Gbps 기반의 파장 분할 다중화 방식 광통신에 사용하기에 충분한 성능을 보였으며, 이를 통해 최근 개발된 상호 위상 변조 방식(XPM Cross Phase Modulation)의 다채널 파장 변환기와 비교해 상대적으로 간단한 구조를 가지고 제작 및 변조 효율에 우위를 보이는 파장 변환기로서 대체될 수 있음을 밝힌다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.201-204
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• 2000

In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

• 전자공학회논문지A
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• 제31A권3호
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• pp.18-27
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• 1994

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.857-860
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• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.

• Journal of Power Electronics
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• 제11권2호
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• 정보학연구
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• 제4권4호
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• pp.51-63
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• 2001

잉여수계(Residue Number System)는 각 모듈러스에 자리올림수의 전달이 필요 없고, 병렬 구조를 이루므로, 디지털 신호처리 및 신경망 처리기와 같은 전용 프로세서 설계에서 사용된다. 그러나, 크기 비교 및 부호 검출시에 혼합기수변환(Mixed Radix Conversion)이 요구되며, 이는 전체 연산 속도를 저해하는 요인이 된다. 그러므로 본 논문에서는 혼합기수 변환의 속도를 향상시키기 위하여 잉여수 분할 방법을 개선한 혼합기수변환기를 설계하였다. 설계된 변환기는 기존의 변환기에 비하여 연산기의 크기는 증가하지만 연산시간은 최대 2배가 향상되었다.

• 정보학연구
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• 제12권2호
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• pp.39-47
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• 2009

Residue Number System is used for the purpose of increasing the speed of processing in the many application parts of Image Processing, Computer Graphic, Neural Computing, Digital Signal Processing etc, since it has the characteristic of parallelism and no carry propagation at each moduli. DRNS has the twice RNS Conversion, it is used to decreases the size of the operator in RNS. But it has a week point on the Second Residue to First Residue Conversion time. So, in this paper SRTFR(Second Residue to First Residue) Converter using MRC(Mixed Radix Conversion) is designed to decrease the size of RTB(Residue to Binary) Converter. Since the proposed SRTFR Converter using MRC(Mixed Rdix Convertion) has a pipeline processing. Also, modular operation is applied to at each partitioned SAM(Subtraction and Addition) and MA(Multiplication and addition). In the following study, the more effective design on MA is needed.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2002년도 학술대회논문집
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• pp.157-163
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• 2002

Consideration for parallel operation in a high power system has been increased due to the advantages of parallel operation like as high productivity, simplicity of design, and redundancy of power. This paper discussed the parallel operation of DC-DC Converter, Which Can be used as a high power system, is studied. Based on the small signal model of DC-DC Converter, the simple and exact power stage model of parallel operation system is derived and the parallel operation system using current balance method for the uniform current distribution among the parallel operation system is discussed. To verify the high performance of the proposed DC-DC converter system for parallel operation, the simulation test of the parallel operation, which has 2 Converter modules, is accomplished.