• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.555-559
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• 2008

Junction temperature of quantum dot laser diodes is investigated by utilizing forward voltage-temperature method. In the case of ridge type laser diodes with deep mesa the increasing rate of junction temperature to current is about 0.05 K/mA, while in the case of shallow mesa the increasing rate is about 0.07 K/mA. It is explained that the relatively low increasing rate in the deep mesa results from the heat expansion to the lateral direction of mesa.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.37-42
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• 2004

Shallow $p^{＋}$-n junctions were formed by preamorphization, low-energy ion implantation and dual-step annealing processes. Germanium ions were implanted into silicon substrates for preamorphization. The dopant implantation was performed into the preamorphized and non-preamorphized substrates using B $F_2$2 ions. Rapid thermal anneal (RTA) and furnace anneal (FA) were employed for dopant activation and damage removal. Samples were annealed by one of the following four methods; RTA(75$0^{\circ}C$/10s)＋Ft FA＋RTA(75$0^{\circ}C$/10s), RTA(100$0^{\circ}C$/10s)＋FA, FA＋The Ge Preamorphized sample exhibited a shallower junction depth than the non-preamorphized sample. When the employed RTA temperature was 100$0^{\circ}C$, FA＋RTA annealing sequence exhibited better junction characteristics than RTA＋FA thermal cycle from the viewpoint of junction depth, sheet resistance, $R_{s}$$.$ $x_{j}$, and leakage current.t.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.414-423
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• 2007

Field Emission Display(FED) has significant advantages over existing display technologies, particularly in the area of small and high quality display. In order to test the feasibility of fabricating the System-on-Chip(SOC) with FED, we conducted the experiment to use the p-n junction as an electron beam source for the flat panel display. A novel structure was constructed to form p-n junctions by generating inversion layer with the electric field from the cantilever style gate. When we applied more than 220V at the cantilever style gate which has a height of $1{\mu}m$, avalanche breakdown onset was successfully achieved. The characteristics was compared with the electron emission from the ultra shallow junction in the avalanche region. The experiment result and the future direction were discussed.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.166-166
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• 2003

Si (100) 기판위에서 에피텍셜하게 자란 CoSi$_2$층은 우수한 열적안정성, 낮은 junction leakage, ultra-Shallow junction형성 등의 장점으로 인하여 많은 주목을 받아왔다. 그래서 에피텍셜 CoSi$_2$층을 형성하기 위한 많은 방법들이 보고되어 왔다. 그 방법으로는 Ti나 TiN층을 이용한 interlayer mediated epitaxy, Co의 제한적 공급을 통한 molecular beam epitaxy와 molecular beam allotaxy, 그리고 금속유기소스를 이용한 반응성화학기상증착법등이 있다. 하지만 이 방법들은 복잡한 증착공정과 열처리 후 잔류층 제거의 어려움등을 가지고 있다. 본 연구는 일반적으로 사용되는 Ti나 oxide의 중간층없이 에피층을 형성시키는 새로운 방법으로 CO-O-N 박막으로부터 열처리에 의해 확산된 Co로부터 CoSi$_2$에피층을 형성시켰다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.51-58
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• 1995

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si cosumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the cosumed Si source during Ti silicidation. This method was applied to the actual fabrication of PMOSFET through SES (selectricely etched Si) techology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.102-106
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• 2005

A low dark current CMOS image sensor (CIS) pixel without any process modification is developed. Dark current is mainly generated at the interface region of shallow trench isolation (STI) structure. Proposed pixel reduces the dark current effectively by separating the STI region from the photodiode junction using simple layout modification. Test sensor array that has both proposed and conventional pixels is fabricated using 0.18 m CMOS process and the characteristics of the sensor are measured. The result shows that the dark current of the proposed pixel is 0.93fA/pixel that is two times lower than the conventional design.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1615-1617
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• 2002

본 논문은 얇은 실리콘 산화막 트렌치를 이용하여 같은 항복 전압에서 면적을 줄이는 접합 마감(junction termination)을 제안하였다. 제안된 P+FLR(Floating Field Ring) 구조는 기존 P+ FLR구조에 비해 항복 전압 571 V에서 면적을 83 %로 감소시켜 접합 마감 특성이 개선되었다.

• Nuclear Engineering and Technology
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• v.5 no.1
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• pp.13-19
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• 1973

The photovoltaic and the electronvoltaic cells have been obtained by forming Sb-implanted n- on p-type and In-implanted p- on n-type silicon p-n junctions Such shallow implantations into silicon wafers due to each dopant were done by the VDH-Implanter. The two types of the silicon p-n junction for these cells have shown special features on their various characteristics to be fitted for the direct energy conversions. The results of the comparative study on both of these cells are described in this article.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.8
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• pp.587-595
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• 1998

Transient thermal analysis simulations are carried out using a modeling program to understand the human body model HBM ESD. The devices were simulated a one-dimensional device subjected to ESD stress by solving Poison's equation, the continuity equation, and heat flow equation. A ramp rise with peak ESD voltage during rise time is applied to the device under test and then discharged exponentially through the device. LDD and NMOS structures were studied to evaluate ESD performance, snap back voltages, device heating. Junction heating results in the necessity for increased electron concentration in the space charge region to carry the current by the ESD HBM circuit. The doping profile adihacent to junction determines the amount of charge density and magnitude of the electric field, potential drop, and device heating. Shallow slopes of LDD tend to collect the negative charge and higher potential drops and device heating.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.89-98
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• 1992

IIM(Implantation Into Metal) process usning Co silicides has been investigated to obtain ultra-shallow junctions less than 0.1$\mu$m. Rapid Thermal Annealing using halogen lamps was employed to form CoSi$_2$ and junctions simultaneously.. Resistivities of CoSi$_2$ were 13-17$\mu$ $\Omega$-cm. CoSi$_2$/p$^{+}$/Si and CoSi$_2$/n$^{+}$/Si junction were formed by diffusion of B and As, respectively, from Co film. It was found out that B and As were severely lost by the evaporation during high temperature annealing Therefore SiO$_2$ capping layers were introduced to prevent the evaporation of the implanted dopants from the films. Investigation of the behavior of dopants with respect to annealing time revealed that increasing the annealing time enhanced the diffusion of dopants into Si from CoSi$_2$.