• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.220-223
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• 2002

The digital logic systems(DLS) is classified into digital combinational logic systems(CDLS) and digital sequential logic systems(SDLS). This paper presents a method of constructing the digital sequential logic systems without feedback. Firstly we assign all elements in Finite Fields to P-valued digit codes using mathematical properties of Finine Fields. Also, we discuss the operarional properties of the building block T-gate that is used to realizing digital sequential logic systems over Finite Fields. Then we realize the digital sequential logic systems without feedback. This digital sequential logic systems without feedback is constructed ny following steps. Firstly, we assign the states in the state-transition diagram to state P-valued digit dodo, then we obtain the state function and predecessor table that is explaining the relationship between present state and previous states. Next, we obtained the next-state function and predecessor table. Finally, we realize the circuit using T-gate and decoder.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.421-426
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• 2010

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.75-84
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• 1995

Fault simulators are used for accurate evaluation of fault coverages of digital circuits. But fault simulation becomes time and memory consuming job because computation time is proportional to wquare of size of circuits. Recently, several approximate algorithms for testability analysis have been published to cope with the problems. COP is very fast but cannot be used for sequential circuits, while STAFAN can ve used for sequential circuits but requires large amount of computation because it utilizes logic simulation results. In this paper EXTASEC(An Extension of Testability Analysis for Sequential Circuits) is proposed. It is an extension of COP in the sense that it is the same as COP for combinational circuits, but it can handle sequential circuits, Xicontrollability and backward line analysis are key concept for EXTASEC. Performance of EXTASEC is proven by comparing EXTASEC with a falut simulator, STAFAN, and COP for ISCAS circuits, and the result is demonstated.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.6 no.3
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• pp.210-216
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• 2006

In the rule based modeling, data partitioning plays crucial role be cause partitioned sub data set implies particular information of the given data set or system. In this paper, we present an empirical study result of the data pattern estimation to find underlying data patterns of the given data. Presented method performs crisp type clustering with given n number of data samples by means of the sequential agglomerative hierarchical nested model (SAHN). In each sequence, the average value of the sum of all inter-distance between centroid and data point. In the sequel, compute the derivation of the weighted average distance to observe a pattern distribution. For the final step, after overall clustering process is completed, weighted average distance value is applied to estimate range of the number of clusters in given dataset. The proposed estimation method and its result are considered with the use of FCM demo data set in MATLAB fuzzy logic toolbox and Box and Jenkins's gas furnace data.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.79.6-79
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• 2002

We propose here sequential 2 methods for obtain information of current or potential data for power transmission line. One is a digital data transmission unit, this is, an output of a current sensor of power transmission line is digitalized by use of an easy asynchronous protocol. The unit has high speed transform rate, easy making header caused of consisting of only logic circuit. The other is, the output of the unit is transformed via LAN interface and displayed on a personal computer. We have confirmed remote measuring using the method for 100A and 240 A of the current information of power transmission line. Therefore we will be able to see a current waveform by use of internet at a cheep c...

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.3
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• pp.75-83
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• 2011

Cognitive radio (CR) technology is to maximize the spectrum utilization by allocating the unused spectrums to the unlicensed users. This technology enables the sharing of channels among secondary (unlicensed) and primary (licensed) users on a non-interference basis after sensing the vacant channel and as a result, it is possible to harness wireless frequency more efficiently. To enhance the accuracy of sensing, RDSS was suggested. It is a fusion mechanism based on the reputation of sensing nodes and WSPRT (weighted sequential probability ratio test). However, in RDSS, the execution number of WSPRT could increase according to the order of inputted sensing values, and the fast defense against the forged values is difficult. In this paper, we propose a transaction signing-based authentication scheme for secure distributed spectrum sensing to response the forged values. The validity of proposed scheme is provided by BAN logic.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2490-2492
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• 2001

According to the appearance of various virtual websites using multimedia technologies for engineering education, the internet applications in engineering education have drawn much interests. But unidirectional communication, simple text/image-based webpages and tedious learning process without motivation etc. have made the lowering of educational efficiency in cyberspace. Thus, to cope with these difficulties this paper presents a web-based educational Java applets for understanding the principles or conceptions of digital logic systems. The proposed Java applets provides the improved learning methods which can enhance the interests of learners. The results of this paper can be widely used to improve the efficiency of cyberlectures in the cyber university. Several sample Java applets are illustrated to show the validity of the proposed learning method.