• Title/Summary/Keyword: sensor layout

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Vision Sensor-Based Driving Algorithm for Indoor Automatic Guided Vehicles

  • Quan, Nguyen Van;Eum, Hyuk-Min;Lee, Jeisung;Hyun, Chang-Ho
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.13 no.2
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    • pp.140-146
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    • 2013
  • In this paper, we describe a vision sensor-based driving algorithm for indoor automatic guided vehicles (AGVs) that facilitates a path tracking task using two mono cameras for navigation. One camera is mounted on vehicle to observe the environment and to detect markers in front of the vehicle. The other camera is attached so the view is perpendicular to the floor, which compensates for the distance between the wheels and markers. The angle and distance from the center of the two wheels to the center of marker are also obtained using these two cameras. We propose five movement patterns for AGVs to guarantee smooth performance during path tracking: starting, moving straight, pre-turning, left/right turning, and stopping. This driving algorithm based on two vision sensors gives greater flexibility to AGVs, including easy layout change, autonomy, and even economy. The algorithm was validated in an experiment using a two-wheeled mobile robot.

Stochastic DLV method for steel truss structures: simulation and experiment

  • An, Yonghui;Ou, Jinping;Li, Jian;Spencer, B.F. Jr.
    • Smart Structures and Systems
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    • v.14 no.2
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    • pp.105-128
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    • 2014
  • The stochastic damage locating vector (SDLV) method has been studied extensively in recent years because of its potential to determine the location of damage in structures without the need for measuring the input excitation. The SDLV method has been shown to be a particularly useful tool for damage localization in steel truss bridges through numerical simulation and experimental validation. However, several issues still need clarification. For example, two methods have been suggested for determining the observation matrix C identified for the structural system; yet little guidance has been provided regarding the conditions under which the respective formulations should be used. Additionally, the specific layout of the sensors to achieve effective performance with the SDLV method and the associated relationship to the specific type of truss structure have yet to be explored. Moreover, how the location of truss members influences the damage localization results should be studied. In this paper, these three issues are first investigated through numerical simulation and subsequently the main results are validated experimentally. The results of this paper provide guidance on the effective use of the SDLV method.

Design of a Capacitive Detection Circuit using MUX and DLC based on a vMOS (vMOS 기반의 DLC와 MUX를 이용한 용량성 감지회로)

  • Jung, Seung-Min
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.4
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    • pp.63-69
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    • 2012
  • This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

Design of a single-pixel photon counter using a self-biased folded cascode operational amplifier (자체 바이어스를 갖는 Folded Cascode OP Amp를 사용한 Single Pixel Photon Counter 설계)

  • Jang, Ji-Hye;Hwang, Yoon-Guem;Kang, Min-Cheol;Jeon, Sung-Chae;Huh, Young;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.05a
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    • pp.678-681
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    • 2009
  • A single-pixel photon counter is designed using a folded cascode CMOS operational amplifier which is self-biased. Since there is no need for a voltage bias circuit, the layout area and power consumption of the designed counter are reduced. The signal voltage of the designed charge sensitive amplifier (CSA) with the MagnaChip $0.18{\mu}m$ CMOS process is simulated to be 138mv, near the theoretical voltage of 151mV. And the layout area of the designed counter is $100{\mu}m{\times}100{\mu}m$.

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Sharing Error Allowances for the Analysis of Approximation Schemes (근사접근법 분석을 위한 오차허용치의 분배방법)

  • Kim, Joon-Mo;Goo, Eun-Hee
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.5
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    • pp.1-7
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    • 2009
  • When constructing various mobile networks including sensor networks, the problem of finding the layout or graph to interconnect the terminals or nodes of the network may come up. Providing a common scheme that can be applied to the kind of problems, and formulating the bounds of the run time and the result of the algorithm from the scheme, one may evaluate precisely the plan of constructing analogous network systems. This paper, dealing with EMST(Euclidean Minimum Spanning Tree) that represents such problems, provides the scheme for constructing EMST by parallel processing over distributed environments, and the ground for determining the maximum difference of the layout or the graph produced from the scheme: the difference from EMST. In addition, it provides the upper bound of the run time of the algorithm from the scheme.

Crack Source location Technique for nam Concrete Beam using Acoustic Emission (음향방출을 이용한 무근콘크리트 보의 균열 발생원 탐사기법)

  • 한상훈;이웅종;조홍동;김동규
    • Journal of the Korea Concrete Institute
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    • v.13 no.2
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    • pp.107-113
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    • 2001
  • This study was conducted preliminarily to develop the crack source location technique for plain concrete beam using acoustic emission(AE). Before the main experiment, the test of virtual An source location was achieved in plain concrete block. The sensor layout was mutually compared between triangular layout and rectangular layout. As the results of test, AE source location by triangular layout was evaluated more effective than that by rectangular layout. The specimen to apply he source location technique was man in total nine specimens (each three in 40 %, 50%, 60% of W/C ratio) which the experiment variable was the compressive strength level(W/C ratio). The bending loading method is selected by cyclic loadings to evaluate the degree of concrete damage. It is seen that Kaiser effect and Felicity effect exists through analysis of AE parameters in coming failure experiment. As a result of analyzing the felicity ratio(FR) values, it is shown that this values can be used for evaluating the degree of concerto damage. AE activity is started highly at the 70% of failure load without the compressive strength level. Thus considered by a index in constructing the system of the failure warning at application of the field structure. And the results compared the real cracking location with the source location has perceived by AE monitoring before it is appeared the primary crack by visual observation.

Vision chip for edge detection with resolution improvement through simplification of unit-pixel circuit (단위 픽셀 회로의 간소화를 통해서 해상도를 향상시킨 이차원 윤곽 검출용 시각칩)

  • Sung, Dong-Kyu;Kong, Jae-Sung;Hyun, Hyo-Young;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.17 no.1
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    • pp.15-22
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    • 2008
  • When designing image sensors including a CMOS vision chip for edge detection, resolution is a significant factor to evaluate the performance. It is hard to improve the resolution of a bio-inspired CMOS vision using a resistive network because the vision chip contains many circuits such as a resistive network and several signal processing circuits as well as photocircuits of general image sensors such as CMOS image sensor (CIS). Low resolution restricts the use of the application systems. In this paper, we improve the resolution through layout and circuit optimization. Furthermore, we have designed a printed circuit board using FPGA which controls the vision chip. The vision chip for edge detection has been designed and fabricated by using $0.35{\mu}m$ double-poly four-metal CMOS technology, and its output characteristics have been investigated.

Parametric study on multichannel analysis of surface waves-based nondestructive debonding detection for steel-concrete composite structures

  • Hongbing Chen;Shiyu Gan;Yuanyuan Li;Jiajin Zeng;Xin Nie
    • Steel and Composite Structures
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    • v.50 no.1
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    • pp.89-105
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    • 2024
  • Multichannel analysis of surface waves (MASW) method has exhibited broad application prospects in the nondestructive detection of interfacial debonding in steel-concrete composite structures (SCCS). However, due to the structural diversity of SCCS and the high stealthiness of interfacial debonding defects, the feasibility of MASW method needs to be investigated in depth. In this study, synthetic parametric study on MASW nondestructive debonding detection for SCCSs is performed. The aim is to quantitatively analyze influential factors with respect to structural composition of SCCS and MASW measurement mode. First, stress wave composition and propagation process in SCCS are studied utilizing 2D numerical simulation. For structural composition in SCCS, the thickness variation of steel plate, concrete core, and debonding defects are discussed. To determine the most appropriate sensor arrangement for MASW measurement, the effects of spacing and number of observation points, along with distances between excitation points, nearest boundary, as well as the first observation point, are analyzed individually. The influence of signal type and frequency of transient excitation on dispersion figures from forwarding analysis is studied to determine the most suitable excitation signal. The findings from this study can provide important theoretical guidance for MASW-based interfacial debonding detection for SCCS. Furthermore, they can be instrumental in optimizing both the sensor layout design and signal choice for experimental validation.

Application of Dielectric Sensor for Soil Moisture Measurement (토양 수분 측정을 위한 유전율식 쎈서 연구)

  • Oh, Yong-Taeg;Oh, Dong-Shig;Song, Kwan-Cheol;Shin, Jae-Sung;Im, Jung-Nam
    • Korean Journal of Soil Science and Fertilizer
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    • v.31 no.2
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    • pp.85-94
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    • 1998
  • Due to relatively high permittivity of water in soils, we placed the soil condenser into soils to measure the soil moisture content. The soil condenser was made with two insulated iron sticks. The capacitance of the soil condenser was determined by the pulse period from RC type oscillation circuit and the highest voltage output accepting 10MHz pulse. After zero point adjustment, the measured relative capacitance percentage (RCS) to the standard condenser obtained by the oscillation circuit almost linearly correlated with the end depth of the sensor submerged in water. The RC type oscillation was disturbed by many sensor installed in a close distance in one place, presumably resulting in that the sensor sticks played as a interfering antennas generating or accepting electron waves from them. The temperature dependance of the output from the sensors could be corrected through experimentally determined revision function. Although lineal correlation was found between soil moisture and RCS, users should derive their own correlation function for every sensor to measure soil moisture, because the outputs were influenced by the installation depth and layout in the soil. The voltage type sensor responded inversely with soil moisture content and so was not suitable to the accurate measurement of soil moisture, but allows high economic benefit in various application such as simplified measurement of soil moisture and irrigation line control because of its low component count. The voltage type moisture sensor could be reinforced by relay controlling circuit to open and to close the solenoid valves respectively at optimal limits of the least and the most soil moisture according to user's adjustment.

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A Design of Digital CMOS X-ray Image Sensor with $32{\times}32$ Pixel Array Using Photon Counting Type (포톤 계수 방식의 $32{\times}32$ 픽셀 어레이를 갖는 디지털 CMOS X-ray 이미지 센서 설계)

  • Sung, Kwan-Young;Kim, Tae-Ho;Hwang, Yoon-Geum;Jeon, Sung-Chae;Jin, Seung-Oh;Huh, Young;Ha, Pan-Bong;Park, Mu-Hun;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1235-1242
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    • 2008
  • In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.