• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.412-418
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• 2009

This study aims to develop a system that enables 20 to 25 wafers to be automatically aligned at the position of the corresponding serial number and facilitates the checkout of wafer processing by sensing them before and after semiconductor processing. It also suggests compensation algorithm and stepper motor control algorithm that carefully align notches. This study minimizes the rate of occurrence by adopting materials of which the surface has proper coefficient of friction when wafers are rotating and that do not rarely produce particles. This study completed the development of a slip resistance apparatus and carried out performance tests through mathematical verification. This system is expected to improve semiconductor yield due to anti-pollution technology in semiconductor processing and can be selectively applied to a large size wafer over 450mm in the future.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• International Journal of Quality Innovation
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• v.7 no.2
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• pp.141-156
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• 2006

This study describes a novel algorithm for optimizing the quality yield of silicon wafer slicing. 12 inch wafer slicing is the most difficult in terms of semiconductor manufacturing yield. As silicon wafer slicing directly impacts production costs, semiconductor manufacturers are especially concerned with increasing and maintaining the yield, as well as identifying why yields decline. The criteria for establishing the proposed algorithm are derived from a literature review and interviews with a group of experts in semiconductor manufacturing. The modified Delphi method is then adopted to analyze those results. The proposed algorithm also incorporates the analytic hierarchy process (AHP) to determine the weights of evaluation. Additionally, the proposed algorithm can select the evaluation outcomes to identify the worst machine of precision. Finally, results of the exponential weighted moving average (EWMA) control chart demonstrate the feasibility of the proposed AHP-based algorithm in effectively selecting the evaluation outcomes and evaluating the precision of the worst performing machines. So, through collect data (the quality and quantity) to judge the result by AHP, it is the key to help the engineer can find out the manufacturing process yield quickly effectively.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.22 no.1
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• pp.9-19
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• 2012

Objectives: The aim of this study is to critically review the exposure surrogates and estimates used to associate health effects in wafer fabrication workers such as spontaneous abortion and cancer, as well as to identify the limitations of retrospective exposure assessment methods Methods: Epidemiologic and exposure-assessment studies of wafer fabrication operations in the semiconductor industry were collected. Retrospective exposure-assessment methods used in cancer risk and mortality and reproductive toxicity were reviewed. Results: Eight epidemiologic papers and two reports compared cancer risk among workers in wafer fabrication facilities in the semiconductor industry with the risk of the general population. Exposure surrogates used in those cancer studies were fabrication(vs. non-fabrication), employment duration, manufacturing eras, job title (operator vs. maintenance worker) and qualitative classifications of agents without assessing specific agent or job-specific exposure. In contrast, specific operation, job title and agents were used to classify the exposure of fabrication workers, contributing to finding a significant association with spontaneous abortion (SAB). Conclusion: Further epidemiologic studies of fabrication workers using more refined exposure assessment methods are warranted in order to examine the associations between fabrication work, environment, and specific agents with cancer risk or mortality as used in SAB epidemiologic studies.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.119-124
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• 2021

In a situation where Moore's law, which states that the performance of semiconductor integrated circuits doubles every two years, is showing a limit from a certain point, and it is difficult to increase the performance due to the limitations of exposure technology.In this study, a wafer hybrid method that can increase the degree of integration Various research on bonding technology is currently in progress. In this study, in order to achieve rotational precision between wafers in wafer hybrid bonding technology, modeling of θ_z alignment stage and VCM actuator modeling used for rotational alignment, magnetic field analysis and desgin, control, and evaluation are performed. The system of this study was controlled by VCM actuator, capactive sensor, and dspace, and the working range was ±7200 arcsec, and the in-position and resoultion were ±0.01 arcsec. The results of this study confirmed that safety and precise control are possible, and it is expected to be applied to the process to increase the integration.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.46 no.2
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.8-13
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• 2023

High bandwidth memory a core technology of the future memory semiconductor industry, is attracting attention. Temporary bonding and debonding process technology, which plays an important role in high bandwidth memory process technology, is also being studied. In this process, total thickness variation is a major factor determining wafer performance. In this study, the reliability of the equipment measuring total thickness variation is identified, and the servo motor settling, and wafer total thickness variation measurement accuracy are analyzed. As for the experimental variables, vacuum, acceleration time, and speed are changed to find the most efficient value by comparing the stabilization time. The smaller the vacuum and the larger the radius, the longer the settling time. If the radius is small, high-speed rotation performance is good, and if the radius is large, low-speed rotation performance is good. In the future, we plan to conduct an experiment to measure the entire of the wafer.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.6
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• pp.572-578
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• 2015

Yield prediction is one of the most important issues in semiconductor manufacturing. Especially, for a fast-changing environment of the semiconductor industry, accurate and reliable prediction techniques are required. In this study, we propose a prediction model to predict wafer yield based on virtual metrology process parameters in semiconductor manufacturing. The proposed prediction model addresses imbalance problems frequently encountered in semiconductor processes so as to construct reliable prediction model. The effectiveness and applicability of the proposed procedure was demonstrated through a real data from a leading semiconductor industry in South Korea.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.149-152
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• 2004

Generally the wafer is increased by 300mm. We are desired that the wafer is prevented from pollutions of metal contaminant on surface of wafer. We have to develop new wafer cleaning process of IC Manufacturing that can reduce DI water and chemical by removal of the wafer cleaning process step. Moreover, it is difficult to control temprature and density of chemical in spite of rapidly increasing automation of system. We design smart module controller for new generation of semiconductor wet station with intelligent algorithm using data that is taken by computer simulation for optimal system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.860-864
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• 2003

Recently. use of compound semiconductor is widely increasing in the area of LED and RF device. In this study, wafer bonding module is designed and optimized to bond 6 inches device wafer and carrier wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Load spreader and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analyses show the designed mechanisms are very effective in performance improvement.