• 한국안전학회지
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• 제31권3호
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• pp.42-46
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• 2016

In LCD Display or semiconductor manufacturing processes, the anti-static technology of glass substrates and wafers becomes one of the most difficult issues which influence the yield of the semiconductor manufacturing. In order to overcome the problems of wafer surface contamination various issues such as ionization in decompressed vacuum and inactive gas(i.e. $N_2$ gas, Ar gas, etc.) environment should be considered. Soft X ray radiation is adequate in air and $O_2$ gas at atmospheric pressure while UV radiation is effective in $N_2$ gas Ar gas and at reduced pressure. At this point of view, the "vacuum ultraviolet ray ionization" is one of the most suitable methods for static elimination. The vacuum ultraviolet can be categorized according to a short wavelength whose value is from 100nm to 200nm. this is also called as an Extreme Ultraviolet. Most of these vacuum ultraviolet is absorbed in various substances including the air in the atmosphere. It is absorbed substances become to transit or expose the electrons, then the ionization is initially activated. In this study, static eliminator based on the vacuum ultraviolet ray under the above mentioned environment was tested and the results show how the ionization performance based on vacuum ultraviolet ray can be optimized. These vacuum ultraviolet ray performs better in extreme atmosphere than an ordinary atmospheric environment. Neutralization capability, therefore, shows its maximum value at $10^{-1}{\sim}10^{-3}$ Torr pressure level, and than starts degrading as pressure is gradually reduced. Neutralization capability at this peak point is higher than that at reduced pressure about $10^4$ times on the atmospheric pressure and by about $10^3$ times on the inactive gas. The introductions of these technology make it possible to perfectly overcome problems caused by static electricity and to manufacture ULSI devices and LCD with high reliability.

• 한국정보전자통신기술학회논문지
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• 제13권1호
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• pp.64-71
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• 2020

전력 반도체 소자의 게이트 구동 칩의 아날로그 회로를 트리밍하기 위해서는 eFuse OTP IP가 필요하다. 기존의 NMOS 다이오드 형태의 eFuse OTP 셀은 셀 사이즈가 작은 반면 DNW(Deep N-Well) 마스크가 한 장 더 필요로 하는 단점이 있다. 본 논문에서는 CMOS 공정에서 추가 공정이 필요 없으면서 셀 사이즈가 작은 PMOS-다이오드 형태의 eFuse OTP 셀을 제안하였다. 본 논문에서 제안된 PMOS-다이오드 형태의 eFuse OTP 셀은 N-WELL 안에 형성된 PMOS 트랜지스터와 기억소자인 eFuse 링크로 구성되어 있으며, PMOS 트랜지스터에서 기생적으로 만들어지는 pn 접합 다이오드를 이용하였다. 그리고 PMOS-다이오드 형태의 eFuse 셀 어레이를 구동하기 위한 코어 구동회로를 제안하였으며, SPICE 모의실험 결과 제안된 코어 회로를 사용하여 61㏀의 post-program 저항을 센싱하였다. 한편 0.13㎛ BCD 공정을 이용하여 설계된 PMOS-다이오드 형태의 eFuse OTP 셀과 512b eFuse OTP IP의 레이아웃 사이즈는 각각 3.475㎛ × 4.21㎛ (=14.62975㎛2)과 119.315㎛ × 341.95㎛ (=0.0408㎟)이며, 웨이퍼 레벨에서 테스트한 결과 정상적으로 프로그램 되는 것을 확인하였다.

• 마이크로전자및패키징학회지
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• 제28권3호
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• pp.9-15
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• 2021

최근 반도체 소자의 소형화는 물리적 한계에 봉착했으며, 이를 극복하기 위한 방법 중 하나로 반도체 소자를 수직으로 쌓는 3D 패키징이 활발하게 개발되었다. 3D 패키징은 TSV, 웨이퍼 연삭, 본딩의 단위공정이 필요하며, 성능향상과 미세피치를 위해서 구리 본딩이 매우 중요하게 대두되고 있다. 본 연구에서는 대기중에서의 구리 표면의 산화방지와 저온 구리 본딩에 티타늄 나노 박막이 미치는 영향을 조사하였다. 상온과 200℃ 사이의 낮은 온도 범위에서 티타늄이 구리로 확산되는 속도가 구리가 티타늄으로 확산되는 속도보다 빠르게 나타났고, 이는 티타늄 나노 박막이 저온 구리 본딩에 효과적임을 보여준다. 12 nm 티타늄 박막은 구리 표면 위에 균일하게 증착되었고, 표면거칠기(R_q)를 4.1 nm에서 3.2 nm로 낮추었다. 티타늄 나노 박막을 이용한 구리 본딩은 200℃에서 1 시간 동안 진행하였고, 이후 동일한 온도와 시간 동안 열처리를 하였다. 본딩 이후 측정된 평균 전단강도는 13.2 MPa이었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.278-278
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• 2016

Solution-processed metal-oxide semiconductors have been considered as the next generation semiconducting materials for transparent and flexible electronics due to their high electrical performance. Moreover, since the oxide semiconductors show high sensitivity to light illumination and possess persistent photoconductivity (PPC), these properties can be utilized in realizing optical memory devices, which can transport information much faster than the electrons. In previous works, metal-oxide semiconductors are utilized as a memory device by using the light (i.e. illumination does the "writing", no-gate bias recovery the "reading" operations) [1]. The key issues for realizing the optical memory devices is to have high photoconductivity and a long life time of free electrons in the oxide semiconductors. However, mono-layered indium-zinc-oxide (IZO) and mono-layered indium-gallium-zinc-oxide (IGZO) have limited photoconductivity and relaxation time of 570 nA, 122 sec, 190 nA and 53 sec, respectively. Here, we boosted up the photoconductivity and relaxation time using a double-layered IZO/IGZO active layer structure. Solution-processed IZO (top) and IGZO (bottom) layers are prepared on a Si/SiO2 wafer and we utilized the conventional thermal annealing method. To investigate the photoconductivity and relaxation time, we exposed 9 mW/cm2 intensity light for 30 sec and the decaying behaviors were evaluated. It was found that the double-layered IZO/IGZO showed high photoconductivity and relaxation time of 28 uA and 1048 sec.

• 센서학회지
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• 제14권1호
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• pp.22-27
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• 2005

A thermoelectric flow sensor for small quantity of gas flow rate was fabricated using silicon wafer semiconductor process and bulk micromachining technology. Evanohm R alloy heater and chromel-constantan thermocouples were used as a generation heat unit and sensing parts, respectively. The heater and thermocouples are thermally isolated on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$ laminated membrane. The characteristics of this sensor were observed in the flow rate range from 0.2 slm to 1.0 slm and the heater power from 0.72 mW to 5.63 mW. The results showed that the sensitivities $(({\partial}({\Delta}V)/{\partial}(\dot{q}));{\;}{\Delta}V$ : voltage difference, $\dot{q}$ : flow rate) were increased in accordance with heater power rise and decreasing of flow rate.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.36.2-36.2
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• 2009

Low dielectric materials have been great attention in the semiconductor industry to develop high performance interlayer dielectrics with low k for Cu interconnect technology. In our study, the dielectric properties of SiOC /SiO2 thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. Polyphenylcarbosilane was synthesized from thermal rearrangement of polymethylphenylsilane around $350^{\circ}C{\sim}430^{\circ}C$. Characterization of synthesized polyphenylcarbosilane was performed with 29Si, 13C, 1H NMR, FT-IR, TG, XRD, GPC and GC analysis. From FT-IR data, the band at 1035 cm-1 is very strong and assigned to CH2 bending vibration in Si-CH2-Si group, indicating the formation of the polyphenylcarbosilane. Number average of molecular weight (Mn) of the polyphenylcarbosilane synthesized at $400^{\circ}C$ for 6hwas 2, 500 and is easily soluble in organic solvent. SiOC/SiO2 thin film was fabricated on ton-type silicon wafer by spin coating using 30wt % polyphenylcarbosilane incyclohexane. Curing of the film was performed in the air up to $400^{\circ}C$ for 2h. The thickness of the film is ranged from $1{\mu}m$ to $1.7{\mu}m$. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and show a dielectric constant as low as 2.5 without added porosity. The SiOC /SiO2 thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

• 한국세라믹학회지
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• 제42권9호
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• pp.624-630
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• 2005

To investigate the possibility of the $ZrO_2$ buffer layer as the insulator for the Metal-Ferroelectric-Insulator-semiconductor (MFIS) structure, $ZrO_2$ and $SrBi_2Ta_2O_9$ (SBT) thin films were deposited on the P-type Si(111) wafer by the R.F. magnetron-sputtering method. According to the process with and without the post-annealing of the $ZrO_2$ buffer layer and SBT thin film, the diffusion amount of Sr, Bi, Ta elements show slight difference through the Glow Discharge Spectrometer (GDS) analysis. From X-ray Photoelectron Spectroscopy (XPS) results, we could confirm that the post-annealing process affects the chemical binding condition of the interface between the $ZrO_2$ thin film and the Si substrate. Compared to the MFIS structure without the post-annealing of the $ZrO_2$ buffer layer, memory window value of MFlS structure with post-annealing of the $ZrO_2$ buffer layer were considerably improved. The window memory of the Pt/SBT (260 nm, $800^{\circ}C)/ZrO_2$ (20 nm) structure increases from 0.75 to 2.2 V under the applied voltage of 9 V after post-annealing.

• 한국세라믹학회지
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• 제34권3호
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• pp.314-322
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• 1997

극저 유전특성을 갖는 SiO2 에어로겔의 박막화의 층간 절연막으로써의 응용성이 연구되었다. 점도가 10~14cP인 SiO2 폴리머 졸을 이소프로판을 분위기 하에서 1000~7000m으로 p-Si(111) 웨이퍼 상에 스핀코팅한 습윤겔 박막을 25$0^{\circ}C$와 1160 psing 조건에서 초임계건조하여 0.5 g/㎤ 정도의 밀도(78% 기공율) 와 4000~21000$\AA$ 범위의 두께를 갖는 SiO2 에어로겔 박막을 제조하였다. 박막의 두께와 미세구조를 제어할 수 있는 주요 인자는 졸의 농도, 회전속도 및 습윤겔 숙성시간임을 알 수 있었다. SiO2 에어로겔 박막의 유전상수 값은 giga급 이상의 차세대 반도체 소자에 충분히 응용될 수 있을 정도로 낮은 2.0 정도이었다.

• 한국정밀공학회지
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• 제22권12호
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• pp.51-60
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• 2005

This paper describes a robust control scheme for high-speed and long stroke scanning motion of high precision linear motor system consisting of linear motor, air bearing guide and position measurement system using heterodyne interferometer. Nowadays, semiconductor process and inspection of wafer or LCD need high speed and long travel length for their high throughput and extremely small velocity fluctuations or tracking errors. In order to satisfy these conditions, linear motor system are widely used because they have large thrust force and do not need motion conversion mechanisms such as ball screw, rack & pinion or capstan with which the system are burdened. However linear motors have a problem called force ripple. Force ripple deteriorates the tracking performances and makes periodic position errors. So, force ripple must be compensated. To maximize the tracking performance of linear motor system, we propose the control scheme which is composed of a robust control method, Time Delay Controller (TDC) and a feedforward control method, Zero Phase Error Tracking Control (ZPETC) for accurate tracking a given trajectory and an adaptive force ripple compensation (AFC) algorithm fur estimating and compensating force ripple. The adaptive ripple compensation is continuously refined on the basis of tracking error. Computer simulation results based on modeled parameters verify the effectiveness of the proposed control scheme for high-speed, long stroke and high precision scanning motion and show that the proposed control scheme can achieve a sup error tracking performance in comparison to conventional TDC control.

• 한국재료학회지
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• 제22권9호
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• pp.450-453
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• 2012

In crystalline solar cells, the substrate itself constitutes a large portion of the fabrication cost as it is derived from semiconductor ingots grown in costly high temperature processes. Thinner wafer substrates allow some cost saving as more wafers can be sliced from a given ingot, although technological limitations in slicing or sawing of wafers off an ingot, as well as the physical strength of the sliced wafers, put a lower limit on the substrate thickness. Complementary to these economical and techno-physical points of view, a device operation point of view of the substrate thickness would be useful. With this in mind, BC-BJ Si and GaAs solar cells are compared one to one by means of the Medici device simulation, with a particular emphasis on the substrate thickness. Under ideal conditions of 0.6 ${\mu}m$ photons entering the 10 ${\mu}m$-wide BC-BJ solar cells at the normal incident angle (${\theta}=90^{\circ}$), GaAs is about 2.3 times more efficient than Si in terms of peak cell power output: 42.3 $mW{\cdot}cm^{-2}$ vs. 18.2 $mW{\cdot}cm^{-2}$. This strong performance of GaAs, though only under ideal conditions, gives a strong indication that this material could stand competitively against Si, despite its known high material and process costs. Within the limitation of the minority carrier recombination lifetime value of $5{\times}10^{-5}$ sec used in the device simulation, the solar cell power is known to be only weakly dependent on the substrate thickness, particularly under about 100 ${\mu}m$, for both Si and GaAs. Though the optimum substrate thickness is about 100 ${\mu}m$ or less, the reduction in the power output is less than 10% from the peak values even when the substrate thickness is increased to 190 ${\mu}m$. Thus, for crystalline Si and GaAs with a relatively long recombination lifetime, extra efforts to be spent on thinning the substrate should be weighed against the expected actual gain in the solar cell output power.