• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.120-124
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• 2004

본 연구는 Diluted Ceria 입자를 사용한 $SiO_2$(Oxide) CMP 현상에 대한 내용이다. Ceria Slurry의 경우 Silica Slurry와 비교하였을 때 Oxide Wafer 표면과 축합 화학반응을 일으키며 Chemistry Dominant한 CMP Mechanism을 따르고, Wafer Center Removal Rate(RR) Fast 의 특성을 가진다. Ceria Slurry의 문제점인 연마 불균일도를 해결하기 위해 Tribological System을 이용하였다. CMP Tribology는 Pad-Slurry 유막-Wafer의 System을 가지며 윤활막에 작용하는 마찰계수(COF)가 주요 인자이다. Tribology에 적용되는 Stribeck Curve를 통해 Slurry 윤활막의 두께(h) 정도를 예상할 수 있으며, 이 윤활막의 두께를 조절함으로써 Uniformity 향상이 가능하다. 이 Ceria Slurry CMP의 연마 불균일도를 향상시킬 수 있는 방법으로 pH 조절 및 점도 증가가 있다. Ceria 입자 CMP는 분산액의 pH 변화에 강한 작용을 받게 되며 PH5 근방에서 최적화된 Uniformity가 가능하다. 점도를 증가시키는 경우 유막 h가 증가하게 되어 Ceria Slurry의 유동이 균일 분포 상태에 가까워지며 Wafer Uniformity 향상이 가능하다.

• 반도체디스플레이기술학회지
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• 제22권2호
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• pp.17-23
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• 2023

In semiconductor manufacturing processes, a cleaning process is important that can remove sub-micron particles. Conventional wet cleaning methods using chemical have limits in removing nano-particles. Thus, physical forces of a mechanical vibration up to 1 MHz frequency, was tried to aid in detaching them from the substrates. In this article, we developed a 1 MHz quartz megasonic for a bare wafer cleaning using finite element analysis. At first, a 1 MHz megasonic prototype was manufactured. Using the results, a main product which can improve a particle removal performance, was analyzed and designed. The maximum impedance frequency was 992 kHz, which agreed well with the experimental value of 986 kHz (0.6% error). Acoustic pressure distributions were measured, and the result showed that maximum / average was 400.0~432.4%, and standard deviation / average was 46.4~47.3%. Finally, submicron particles were deposited and cleaned for the assessment of the system performance. As a result, the particle removal efficiency (PRE) was proved to be 92% with 11 W power. Reflecting these results, the developed product might be used in the semiconductor cleaning process.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• 반도체디스플레이기술학회지
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• 제8권2호
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• pp.31-35
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• 2009

In the silicon wafer polishing process, the mounting stage of silicon wafer on the ceramic carrier block has been using the polishing template which utilizes the porous surface instead of traditional wax mounting method. Here in this article, the experimental study is carried out in order to study the wafer demounting by water jet and the effects of operating conditions such as the water jet flowrate and the number of water jet nozzles on the wafer demounting time. It is found that the measured wafer demounting time is inversely proportional to the water flowrate per nozzle, regardless of number of nozzles used; implying that the stagnation pressure by the water jet impingement is the dominant key factor. Additionally, by using the transparent disk instead of wafer, the air bubble formation and growth is observed under the disk, making the passage of water flow, and subsequently demounting the wafer from the porous pad.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2032-2037
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• 2007

Numerical analysis was conducted to investigate the atomic layer deposition(ALD) of silicon nitride using silane and ammonia as precursors. The present study simulated the surface reactions for as-deposited $Si_3N_4$ as well as the kinetics for the reactions of $SiH_4$ and $NH_3$on the semiconductor wafer. The present numerical results showed that the ALD process is dependent on the activation constant. It was also shown that the low activation constant leads to the self-limiting reaction required for the ALD process. The inlet and wafer temperatures were 473 K and 823 K, respectively. The system pressure is 2 Torr.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• 대한산업공학회지
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• 제35권4호
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• pp.266-279
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• 2009

This paper focuses on the problem of scheduling wafer lots with limited waiting times between pairs of consecutive operations in a semiconductor wafer fabrication facility. For the problem of minimizing total tardiness of orders, we develop a priority rule based scheduling method in which a scheduling decision for an operation is made based on the states of workstations for the operation and its successor or predecessor operation. To evaluate performance of the suggested scheduling method, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation experiments show that the suggested method performs better than a method suggested in other research and the one that has been used in practice.

• 반도체디스플레이기술학회지
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• 제22권2호
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• pp.81-86
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• 2023

Recently, there has been an increased demand for light-emitting diode (LED) due to the growing emphasis on environmental protection. However, the use of GaN-based sapphire in LED manufacturing leads to the generation of defects, such as dislocations caused by lattice mismatch, which ultimately reduces the luminous efficiency of LEDs. Moreover, most inspections for LED semiconductors focus on evaluating the luminous efficiency after packaging. To address these challenges, this paper aims to detect defects at the wafer stage, which could potentially improve the manufacturing process and reduce costs. To achieve this, image processing and deep learning-based defect detection techniques for Sapphire Epi-Wafer used in Green LED manufacturing were developed and compared. Through performance evaluation of each algorithm, it was found that the deep learning approach outperformed the image processing approach in terms of detection accuracy and efficiency.

• 한국환경보건학회지
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• 제37권1호
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• pp.12-21
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• 2011

The objective of this study is to review retrospective exposure assessment methods used in wafer fabrication operations to determine whether adverse health effects including mortality or cancer incidence are related to employment in particular work activities and to recommend an appropriate approach for retrospective exposure assessment methods for epidemiological study. The goal of retrospective exposure assessment for such studies is to assign each study subject to a workgroup in such a way that differences in exposure within the workgroups are minimized, as well as to maximize the contrasts in exposure between workgroups. To reduce the misclassification of exposure and to determine if adverse health effects including mortality or cancer incidence are related to particular work activities of wafer fabrication workers, a minimum requirement of work history information on the wafer manufacturing eras, job and department at which they were exposed should be assessed. Retrospective assessment of the task that semiconductor workers performed should be conducted to determine not only the effect of a particular job on the development of adverse health effects including mortality or cancer incidence, but also to adjust for the healthy worker effect. In order to identify specific hazardous agents that may cause adverse health effects, past exposure to a specific agent or agent matrices should also be assessed.

• 한국산업보건학회지
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• 제26권1호
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• pp.1-10
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• 2016

Objectives: The aim of this study is to review the results of exposure to chemicals and to extremely low frequency(ELF) magnetic fields generated in wafer fabrication operations in the semiconductor industry. Methods: Exposure assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until the end of 2015. The key words used in the literature search were "semiconductor industry", "wafer fab", "silicon wafer", and "clean room," both singly and in combination. Literature reporting on airborne chemicals and extremely low frequency(ELF) magnetic fields were collected and reviewed. Results and Conclusions: Major airborne hazardous agents assessed were several organic solvents and ethylene glycol ethers from Photolithography, arsenic from ion implantation and extremely low frequency magnetic fields from the overall fabrication processes. Most exposures to chemicals reported were found to be far below permissible exposure limits(PEL) (10% < PEL). Most of these results were from operators who handled processes in a well-controlled environment. In conclusion, we found a lack of results on exposure to hazardous agents, including chemicals and radiation, which are insufficient for use in the estimation of past exposure. The results we reviewed should be applied with great caution to associate chronic health effects.