• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.4
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• pp.415-424
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• 2002

Semiconductor manufacturing has been emerged as a highly competitive but profitable business. Accordingly it becomes very important for semiconductor manufacturing companies to meet customer demands at the right time, in order to keep the leading edge in the world market. However, due-date oriented production is very difficult task because of the complex job flows with highly resource conflicts in fabrication shop called FAB. Due to its cyclic manufacturing feature of products, to be completed, a semiconductor product is processed repeatedly as many times as the number of the product manufacturing cycles in FAB, and FAB processes of individual manufacturing cycles are composed with similar but not identical unit processes. In this paper, we propose a production scheduling and control scheme that is designed specifically for semiconductor scheduling environment (FAB). The proposed scheme consists of three modules: simulation module, cycle due-date estimation module, and dispatching module. The fundamental idea of the scheduler is to introduce the due-date for each cycle of job, with which the complex job flows in FAB can be controlled through a simple scheduling rule such as the minimum slack rule, such that the customer due-dates are maximally satisfied. Through detailed simulation, the performance of a cycle due-date based scheduler has been verified.

• Nuclear Engineering and Technology
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• v.51 no.2
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• pp.439-443
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• 2019

To improve the noise characteristics, software-based noise reduction algorithms are widely used in cadmium zinc telluride (CZT) pixelated semiconductor gamma camera system. The purpose of this study was to develop an improved median filtering algorithm using a thresholding method for noise reduction in a CZT pixelated semiconductor gamma camera system. The gamma camera system simulated is a CZT pixelated semiconductor detector with a pixel-matched parallel-hole collimator and the spatial resolution phatnom was designed with the Geant4 Application for Tomography Emission (GATE). In addition, a noise reduction algorithm with a median filter using an improved thresholding method is developed and we applied our proposed algorithm to an acquired spatial resolution phantom image. According to the results, the proposed median filter improved the noise characteristics compared to a conventional median filter. In particular, the average for normalized noise power spectrum, contrast to noise ratio, and coefficient of variation results using the proposed median filter were 10, 1.11, and 1.19 times better than results using conventional median filter, respectively. In conclusion, our results show that the proposed median filter using improved the thresholding method results in high imaging performance when applied in a CZT semiconductor gamma camera system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.139-145
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• 2014

Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.

• Journal of the Semiconductor & Display Technology
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• v.4 no.1 s.10
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• pp.49-53
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• 2005

The nanoparticle deposition chamber, which is used for quantum dot semiconductor memory applications, is designed by means of numerical simulation. In this research, the numerical simulations for deposition chamber were performed by commercial software, FLUENT. The deposition of nanoparticles is calculated by diffusion force, thermophoresis and electrophoresis of particles. As a results, when the diffusion force was considered, the most of particles deposited in the wall of deposition chamber. But as considering thermophoresis and electrophoresis of particles, the particles were deposited wafer surface, perfectly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.32-40
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• 2004

An extension of the density-gradient model to include the non-local transport effect is presented. The governing equations can be derived from the first three moments of the Wigner distribution function with some approximations. A new nonlinear discretization scheme is applied to the model to reduce the discretization error. We also developed a new boundary condition for the $Si/SiO_2$ interface that includes the electron wavefunction penetration into the oxide to obtain more accurate C-V characteristics. We report the simulation results of a 25-nm metal-oxide-semiconductor field-effect transistor (MOSFET) device.

• Journal of the Korean Society of Industry Convergence
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• v.4 no.3
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• pp.329-337
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• 2001

This simulator is developed for the analysis of a MOSFET based on Thermally Coupled Energy Transport Model(TCETM). The simulator has the ability to calculate not only stationary characteristics but also non - stationary characteristics of a MOSFET. It solves basic semiconductor devices equations including Possion equation, current continuity equations for electrons and holes, energy balance equation for electrons and heat flow equation, using finite difference method. The conventional semiconductor device simulation technique, based on the Drift-Diffusion Model (DDM), neglects the thermal and other energy-related properties of a miniaturized device. I, therefore, developed a simulator based on the Thermally Coupled Energy Transport Model (TCETM) which treats not only steady-state but also transient phenomena of such a small-size MOSFET. In particular, the present paper investigates the breakdown characteristics in transient conditions. As a result, we found that the breakdown voltage has been largely underestimated by the DDM in transient conditions.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1559-1561
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• 2003

In northeast Asia, there will be several important HVDC transmission lines to be established in Korea and China for perspective electric network market. 5500V 4-inches High voltage thyristor can be used in the DC transmission and distribution of electric power system. In this application, many thyristors are connected in series for each thyristor valves. Therefore, the required low reverse-recovery charge QRR and low on-state voltage drop $V_{TM}$ for such thyristor is necessary to this application. In our work, the on-state and off-state voltage performance was simulated by commercial simulation software.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.118-123
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• 2023

Partially magnetized capacitively coupled plasma (CCP) sources are investigated using a two-dimensional kinetic simulation code named EDIPIC-2D. A converging numerical solution was obtained for CCP with a 60 MHz power source, while properly capturing the dynamics of electrons and power absorption over a single RF period. The effects of magnetic fields with different orientations were evaluated. Axial magnetic fields caused changes in the spatial distribution of plasma density, affecting the loss channel. Transverse magnetic fields enhanced stochastic heating near the powered electrode, leading to an increase in plasma density while the significant E×B drift loss compensated for this rise.