• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.86.1-86.1
• /
• 2015

As the feature size of Si-based semiconductor shrinks to nanometer scale, we are facing to the problems such as short channel effect and leakage current. One of the solutions to cope with those issues is to bring III-V compound semiconductors to the semiconductor structures, because III-V compound semiconductors have much higher carrier mobility than Si. However, introduction of III-V semiconductors to the current Si-based manufacturing process requires great challenge in the development of process integration, since they exhibit totally different physical and chemical properties from Si. For example, epitaxial growth, surface preparation and wet etching of III-V semiconductors have to be optimized for production. In addition, oxidation mechanisms of III-V semiconductors should be elucidated and re-growth of native oxide should be controlled. In this study, surface preparation methods of various III-V compound semiconductors such as GaAs, InAs, and GaSb are introduced in terms of i) how their surfaces are modified after different chemical treatments, ii) how they will be re-oxidized after chemical treatments, and iii) is there any effect of surface orientation on the surface preparation and re-growth of oxide. Surface termination and behaviors on those semiconductors were observed by MIR-FTIR, XPS, ellipsometer, and contact angle measurements. In addition, photoresist stripping process on III-V semiconductor is also studied, because there is a chance that a conventional photoresist stripping process can attack III-V semiconductor surfaces. Based on the Hansen theory various organic solvents such as 1-methyl-2-pyrrolydone, dimethyl sulfoxide, benzyl alcohol, and propylene carbonate, were selected to remove photoresists with and without ion implantation. Although SPM and DIO3 caused etching and/or surface roughening of III-V semiconductor surface, organic solvents could remove I-line photoresist without attack of III-V semiconductor surface. The behavior of photoresist removal depends on the solvent temperature and ion implantation dose.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.6-11
• /
• 2011

We have developed dissolved ozone decompose system in the used ozonated water for the semiconductor and LCD fabrication processes, which will be base of obtaining core process technology in the high performance, low price semiconductor and LCD fabrications. Using this technology, it is possible for the semiconductor wafer and LCD planer to process more rapid and chip, and productivity will be improved.

• Journal of the Semiconductor & Display Technology
• /
• v.6 no.4
• /
• pp.49-52
• /
• 2007

As the minimum feature size decrease, control of contamination by nanoparticles is getting more attention in semiconductor process. Cleaning technology which removes nanoparticles is essential to increase yield. A reference wafer on which particles with known size and number are deposited is needed to evaluate the cleaning process. We simulated particle trajectories in the chamber by using FLUENT. Charged monodisperse particles are generated using SMPS (Scanning Mobility Particle Sizer) and deposited on the wafer by electrostatic force. The Experimental results agreed with the simulation results well. We calculate the particles loss in pipe flow theoretically and compare with the experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.04b
• /
• pp.34-37
• /
• 2004

Recently advancing mobile communication tools and I.T industry, semiconductor device is requested more integrated, faster operation time and more scaled-down. Because of these reasons semiconductor device is requested multilayer interconnection. For the multilayer interconnection chemical mechanical polishing (CMP) becomes one of the most useful process in semiconductor manufacturing process. In this experiment, we focus on understand the characterize and improve the CMP technology by control of slurry flow rate. Consequently, we obtain that optimal flow rate of slurry is 170ml/min, since optimal conditions are less chemical flow and performance high with good selectivity to Ta. If we apply this results to copper CMP process. it is thought that we will be able to obtain better yield.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.1
• /
• pp.46-48
• /
• 2015

Thin film transistor (TFT) with silicon indium zinc oxide (SIZO) was fabricated by solution process, and the effect of annealling temperature on the electrical performance has been explored. The performance of SIZO TFT exhibited saturation mobility of $1.37cm^2$/Vs, a threshold voltage of -7.2 V, and an on-off ratio of $1.1{\times}10^5$.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.213-216
• /
• 1988

This paper describes design & fabrication of RF modulator using 2um Bipolar process which convert video & audio signal into high frequency VHF/UHF signals for all TV standards. This VHF/UHF RF modulator fabricated using 2um bipolar process( T max = 5GHz) shows satisfying electrical characteristics and meets all the design targets.

• Journal of the Semiconductor & Display Technology
• /
• v.3 no.2
• /
• pp.11-15
• /
• 2004

Scales, accumulated on some parts of semiconductor equipments such as sputters and CVD during the device fabrication processes, often lower the lifetime of the equipments and production yields. Thus, many equipment parts have be cleaned regularly. In this study, an attempt to establish an effective process to remove scales on the sidewall of collimators located inside the chamber of the sputter was made. The EDX analysis revealed that the scales were composed of Ti and TiN with the columnar structure. Through the trial-and-error experiments, it was found that the etching in the $HNO_3$:$H_2SO_4$:$H_2O$=4:2:4 solution for 5.5 hrs at $67^{\circ}C$, after the oxide removal in the HF solution, and the heat-treatment at $700^{\circ}C$ for 1 min., was the most effective process for the scale removal.

• Journal of the Korean Vacuum Society
• /
• v.19 no.4
• /
• pp.265-274
• /
• 2010

The excellent performance and stability of dry-vacuum-pump is essential to create and maintain high quality vacuum condition in semiconductor and display process. The development of dry-vacuum-pump needs systematic consideration for target application as well as delicate mechanical issues. Here, we introduce a development procedures of dry-vacuum-pump for semiconductor-process-class.

• Journal of the Semiconductor & Display Technology
• /
• v.18 no.4
• /
• pp.1-5
• /
• 2019

This study has been focused on properties of surface technology for large diameter upper electrode using in high density plasma process as like semi-conductor manufacturing process. The experimental studies have been carried out to get mirror surface for upper electrode. For a formation of high surface quality upper electrode, single crystal silicon upper electrode has been mechanical and chemical machining worked. Mechanical machining work of the upper electrode is carried out with varying mesh type using diamond wheel. In case of chemical machining work, upper electrode surface roughness was observed to be strongly dependent upon the etchant. The different surface roughness characteristics were observed according to etchant. The machining result of the surface roughness and surface morphology have been analyzed by use of surface roughness tester, laser microscope and ICP-MS.

• Journal of the Semiconductor & Display Technology
• /
• v.20 no.3
• /
• pp.57-64
• /
• 2021

The domestic semiconductor industry can produce various products that will satisfy customer needs by diversifying assembly parts and increasing compatibility between them. It is necessary to improve the production line as a method to reduce the work-in-process inventory (WIP) in the assembly line, the idle time of the worker, and the idle time of the process. The improvement of the production line is to balance the capabilities of each process as a whole, and to determine the timing of product input or the order of the work process so that the time required between each process is balanced. The purpose of this study is to find the optimal WIP and buffer size through SA (Simulated Annealing) that minimizes lead time while matching the number of two parts in a parallel assembly line with bottleneck process. The WIP level and buffer size obtained by the SA algorithm were applied to the CONWIP and DBR systems, which are the existing production systems, and the simulation was performed by applying them to the new hybrid production system. Here, the Hybrid method is a combination of CONWIP and DBR methods, and it is a production system created by setting new rules. As a result of the Simulation, the result values were derived based on three criteria: lead time, production volume, and work-in-process inventory. Finally, the effect of the hybrid production method was verified through comparative analysis of the result values.