• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Electronics and Telecommunications Trends
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• v.35 no.4
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• pp.1-10
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• 2020

Since the 1960s, semiconductor packaging technology has developed into electrical joining techniques using lead frames or C4 bumps using tin-lead solder compositions based on traditional reflow processes. To meet the demands of a highly integrated semiconductor device, high reliability, high productivity, and an eco-friendly simplified process, packaging technology was required to use new materials and processes such as lead-free solder, epoxy-based non cleaning interconnection material, and laser based high-speed processes. For next generation semiconductor packaging, the study status of two epoxy-based interconnection materials such as fluxing and hybrid underfills along with a laser-assisted bonding process were introduced for fine pitch semiconductor applications. The fluxing underfill is a solvent-free and non-washing epoxy-based material, which combines the underfill role and fluxing function of the Surface Mounting Technology (SMT) process. The hybrid underfill is a mixture of the above fluxing underfill and lead-free solder powder. For low-heat-resistant substrate applications such as polyethylene terephthalate (PET) and high productivity, laser-assisted bonding technology is introduced with two epoxy-based underfill materials. Fluxing and hybrid underfills as next-generation semiconductor packaging materials along with laser-assisted bonding as a new process are expected to play an active role in next-generation large displays and Augmented Reality (AR) and Virtual Reality (VR) markets.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.10
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• pp.103-112
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• 1998

The evolution of semiconductor manufacturing technology has accelerated the reduction of device dimensions and the increase of integrated circuit density. In order to improve yield within a short turn around time and maintain it at high level, a system that can rapidly determine problematic processing steps is needed. The statistical process control detects abnormal process variation of key parameters. Expert systems in SPC can serve as a valuable tool to automate the analysis and interpretation of control charts. A set of IF-THEN rules was used to formalize knowledge base of special causes. This research proposes a strategy to apply expert system to SPC in semiconductor manufacturing. In analysis, the expert system accomplishes the instability detection of process parameter, In diagnosis, an engineer is supported by process analyzer program. An example has been used to demonstrate the expert system and the process analyzer.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.124-128
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• 2023

Semiconductor engineers have long sought to enhance the energy efficiency of mobile semiconductors by reducing their voltage. During the final stages of the semiconductor manufacturing process, the screening and evaluation of voltage is crucial. However, determining the optimal test start voltage presents a significant challenge as it can increase testing time. In the semiconductor manufacturing process, a wealth of test element group information is collected. If this information can be controlled to predict the test voltage, it could lead to a reduction in testing time and increase the probability of identifying the optimal voltage. To achieve this, this paper is exploring machine learning techniques, such as linear regression and ensemble models, that can leverage large amounts of information for voltage prediction. The outcomes of these machine learning methods not only demonstrate high consistency but can also be used for feature engineering to enhance accuracy in future processes.

• Proceedings of the Korean Vacuum Society Conference
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• 1997.02a
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• pp.98-99
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• 1997

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.105-109
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• 2020

Today's placement machines can pick and place thousands of components per hour with a very high degree of accuracy. The packaged semiconductor chips are inserted into a carrier at regular intervals, covered with a tape to protect the chips from external impact, and supplied in a roll form. These packaging processes also progress rapidly in a consistent direction, affecting the peelback strength between the cover tape and carrier depending on the main process conditions. In this paper, we analyzed the main process variables that affect peelback strength in the reel tape packaging process for packaging semiconductor chips. The main effects and interactions were analyzed. The peelback strength range required in the packaging process was set as the nominal the best characteristics, and the optimum process condition satisfying this was derived.

• The Magazine of the IEIE
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• v.35 no.7
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• pp.57-71
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• 2008

The last decade has witnessed great improvements in power semiconductor devices thanks to the advanced design and process, which have made it possible to significantly improve the electrical performances of electronic systems while simultaneously reducing their site, weight and perhaps most importantly reducing their cost. Among the power semiconductor devices, IGBT will be a key semiconductor component for power industry since it has a huge potential to cover large areas of power electronics from small home appliances to heavy industries. Currently, only a few limited power semiconductor manufacturers supply most of the industrial consumptions of power IGBT and its modules. Therefore, a large portion of technology in the power industry is dependent on other advanced countries. In this regard, to independently build power IGBT devices and the relevant power module technology, Korean government initiated a new 5-year project 'Power IT,' which also aimed at booming the business of the power semiconductor and the allied industries. With the success of this power IT project, it is expected that the power semiconductor technology will be a basis to foster the high power semiconductor industry and moreover, there will be more innovative developments in the Korea region and globally Also, forming the channel between the customers and suppliers, it is possible to effectively develop the customized power products, which could strengthen the competitiveness of Korean power industry. Furthermore, the power industry including semiconductor manufacturers will be technologically self-supporting and be able to obtain good business opportunities, and eventually increase the share in the growing power semiconductor market, which could be positioned as a major industry in Korea.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.18-21
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• 2020

Undetected wafer slip during the lift pin-down motion in semiconductor equipment may affect the center to edge variation, wafer warpage, and pattern misalignment in plasma equipment. Direct measuring of the amount of wafer slip inside the plasma process chamber is not feasible because of the hardware space limitation inside the plasma chamber. In this paper, we demonstrated a practice for the wafer lift pin-up and down motions with respect to the gear ratio, operating voltage, and pulse width modulation to maintain accurate wafer position using remote control linear servo motor with an experimentally designed chamber mockup. We noticed that the pin moving velocity and gear ratio are the most influencing parameters to be control, and the step-wised position control algorithm showed the most suitable for the reduction of wafer slip.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.15-18
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• 2002

To achieve the global planarization, CMP Technology has been used to the next generation semiconductor process, and the study made tremendous progress up to date. As the device demension shrinked， CMP Technology has been applied in a various way and more people interested in this field to simplify the process. To attain the goal for safer 0.13um or below 10 nano process, many of those expected task must be solved. By describing this current CMP process issue and future trend for the CMP planarization process, It personally hope that this paper would help to the people who has concerns for the next generation semiconductor manufacturing industry in common.

• Journal of the Semiconductor & Display Technology
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• v.16 no.4
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• pp.68-74
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• 2017

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. Up to now there have been a lot of researches on thermal NIL, but most of them have been focused on polymer deformation in the molding process and there are very few studies on the cooling and demolding process. In this paper a cooling process of the polymer resist in thermal NIL is analyzed with finite element method. The modeling of cooling process for mold, polymer resist and substrate is developed. And the cooling process is numerically investigated with the effects of imprinting temperature and residual layer thickness of polymer resist on stress distribution of the polymer resist. The results show that the lower imprinting temperature, the higher the maximum von Mises stress and that the thicker the residual layer, the greater maximum von Mises stress.