• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.1
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• pp.113-122
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• 1996

As integrity of semiconductor device is increased, accurate and efficient modeling and recipe generation of semiconductor fabrication procsses are necessary. Among the major semiconductor manufacturing processes, dry etc- hing process using gas plasma and accelerated ion is widely used. The process involves a variety of the chemical and physical effects of gas and accelerated ions. Despite the increased popularity, the complex internal characteristics made efficient modeling difficult. Because of difficulty to determine the control input for the desired output, the recipe generation depends largely on experiences of the experts with several trial and error presently. In this paper, the optimal control of the etching is carried out in the following two phases. First, the optimal neural network models for etching process are developed with genetic algorithm utilizing the input and output data obtained by experiments. In the second phase, search for optimal control inputs in performed by means of using the optimal neural network developed together with genetic algorithm. The results of study indicate that the predictive capabilities of the neural network models are superior to that of the statistical models which have been widely utilized in the semiconductor factory lines. Search for optimal control inputs using genetic algorithm is proved to be efficient by experiments. (author). refs., figs., tabs.

• Journal of Korean Institute of Industrial Engineers
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• v.40 no.4
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• pp.404-414
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• 2014

Yield prediction is important to manage semiconductor quality. Many researches with machine learning algorithms such as SVM (support vector machine) are conducted to predict yield precisely. However, yield prediction using SVM is hard because extremely imbalanced and big data are generated by final test procedure in semiconductor manufacturing process. Using SVM algorithm with imbalanced data sometimes cause unnecessary support vectors from major class because of unselected support vectors from minor class. So, decision boundary at target class can be overwhelmed by effect of observations in major class. For this reason, we propose a under-sampling method with minor class based SVM (MCSVM) which overcomes the limitations of ordinary SVM algorithm. MCSVM constructs the model that fixes some of data from minor class as support vectors, and they can be good samples representing the nature of target class. Several experimental studies with using the data sets from UCI and real manufacturing process represent that our proposed method performs better than existing sampling methods.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.444-446
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• 1987

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.65-70
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• 2022

In manufacturing and semiconductor industries, transfer robots increase productivity through accurate and continuous work. Due to the nature of the semiconductor process, there are environments where humans cannot intervene to maintain internal temperature and humidity in a clean room. So, transport robots take responsibility over humans. In such an environment where the manpower of the process is cutting down, the lack of maintenance and management technology of the machine may adversely affect the production, and that's why it is necessary to develop a technology for the machine failure diagnosis system. Therefore, this paper tries to identify various causes of failure of transport robots that are widely used in semiconductor automation, and the Prognostics and Health Management (PHM) method is considered for determining and predicting the process of failures. The robot mainly fails in the driving unit due to long-term repetitive motion, and the core components of the driving unit are motors and gear reducer. A simulation drive unit was manufactured and tested around this component and then applied to 6-axis vertical multi-joint robots used in actual industrial sites. Vibration data was collected for each cause of failure of the robot, and then the collected data was processed through signal processing and frequency analysis. The processed data can determine the fault of the robot by utilizing machine learning algorithms such as SVM (Support Vector Machine) and KNN (K-Nearest Neighbor). As a result, the PHM environment was built based on machine learning algorithms using SVM and KNN, confirming that failure prediction was partially possible.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.275-283
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• 2021

In this study, a driver IC for an AC-powered LED that can be manufactured with a low voltage semiconductor process is designed and the performances of the driver IC were simulated. In order to manufacture a driver IC that operates directly at AC 220V, a semiconductor manufacturing process that satisfies a breakdown voltage of 500V or higher is required. A semiconductor manufacturing process for a high-voltage device requires a much higher manufacturing cost than a general semiconductor process for a low-voltage device. Therefore, the LED driver IC is designed in series so that it can be manufactured with semiconductor process technology that implements a low-voltage device. This makes it possible to divide and apply the voltage to each LED block even if the input voltage is high. The LED lighting circuit shows a power factor of 96% at 220V. In the pnp transistor circuit, a very high power factor of 99.7% can be obtained, and it shows a very stable operation regardless of the fluctuation of the input voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.268-269
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• 2008

We have examined the effect of physical drying and annealing conditions for the soluble derivatives of polythiophene as p-type channel materials of organic thin film transistors (OTFTs) in our special designed drying system; performances of the jetting-processed OTFTs can be improved more than 10 times just by optimizing the physical conditions of drying and annealing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.291-294
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• 1996

We present the experimental results of high quality factor (Q) inductors fabricated on high-resistivity silicon wafer using standard CMOS process without any modificatons such as thick gold layer or multilayer interconnection. This demonstrates the possibility of building high Q inductors using lower cost technologies, compared with previous results using complicated process. The comparative analysis is carried out to find the optimized inductor shape for the maximum performance by varying the thickness of metal and number of turns with rectangular shape.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.4
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• pp.415-424
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• 2002

Semiconductor manufacturing has been emerged as a highly competitive but profitable business. Accordingly it becomes very important for semiconductor manufacturing companies to meet customer demands at the right time, in order to keep the leading edge in the world market. However, due-date oriented production is very difficult task because of the complex job flows with highly resource conflicts in fabrication shop called FAB. Due to its cyclic manufacturing feature of products, to be completed, a semiconductor product is processed repeatedly as many times as the number of the product manufacturing cycles in FAB, and FAB processes of individual manufacturing cycles are composed with similar but not identical unit processes. In this paper, we propose a production scheduling and control scheme that is designed specifically for semiconductor scheduling environment (FAB). The proposed scheme consists of three modules: simulation module, cycle due-date estimation module, and dispatching module. The fundamental idea of the scheduler is to introduce the due-date for each cycle of job, with which the complex job flows in FAB can be controlled through a simple scheduling rule such as the minimum slack rule, such that the customer due-dates are maximally satisfied. Through detailed simulation, the performance of a cycle due-date based scheduler has been verified.