• 제목/요약/키워드: semiconductor materials quality

검색결과 147건 처리시간 0.022초

파워인덕터 생산용 표면 UV 인쇄장치 성능 연구 (A Study on the Performance of Surface UV Printing Device for Power Indicator Production)

  • 이현무;안소미;안성민;서정환;정병조;강성린
    • 미래기술융합논문지
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    • 제2권4호
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    • pp.1-6
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    • 2023
  • 파워인덕터 생산용 표면 UV 인쇄장치 성능 연구는 원기둥 자석의 자력 형성이 상, 하로 형성되게 제작함으로써 제품 고정 시 제품이 뒤집히거나, 세워지는 현상을 방지하는 기술을 적용하여 인쇄 진행 시 품질 소모성 자재(제판, Squeegee)의 파손을 방지하고, 인쇄 품질을 향상시킬 수 있다. 자력의 방향을 바꾼 원기둥 자석의 개발로 파우더 압축으로 제작한 메탈 소재 제품에 대한 고정 방법이 안정화 되어 소형 제품에 대한 생산 능력이 증대할 것이다. 최종적으로 원기둥 자석을 활용한 파워인덕터 표면 UV 인쇄 장치를 연구함으로써, 기존 작업 진행하던 스프레이, Deeping 방식과 차별성을 둘 수 있고, 생산량이 크게 향상될 것이며 결과적으로는 인원 감축으로 원가절감 및 경쟁력 있는 제품 생산을 할 수 있을 것이다.

Pt/$YMnO_3$/$Y_2$$O_3$/Si(MFIS) 구조의 특성에 미치는 ${Y_2}{O_3}$층의 영향 (Effect of ${Y_2}{O_3}$Buffer Layer on the Characteristics of Pt/$YMnO_3$/$Y_2$$O_3$/Si(MFIS) Structure)

  • 양정환;신웅철;최규정;최영심;윤순길
    • 한국재료학회지
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    • 제10권4호
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    • pp.270-275
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    • 2000
  • Metal/ferroelectric/insulator/semiconductor(MFIS)-Field Effect Transistor을 위한 Pt/YMnO$_3$/Y$_2$O$_3$/Si 구조를 제조하여 MFIS 구조의 특성에 미치는 $Y_2$O$_3$박막의 영향을 고찰하였다. PLD법을 이용하여 p=type Si(111) 기판 위에 증착시킨 $Y_2$O$_3$박막은 증착온도와 관계없이 (111)방향으로의 우선배향성을 갖고 결정화 되었다. 실리콘 위에 바로 MOCVD법에 의해 강유전체 YMnO$_3$박막을 증착시킨 경우 실리콘과의 계면에서 Mn이 부족한 층이 형성되지만 $Y_2$O$_3$가 실리콘과 YMnO$_3$사이에 삽입된 경우는 $Y_2$O$_3$바로 위에서부터 화학양론비에 일치하는 양질의 YMnO$_3$박막을 얻을 수 있었다. 85$0^{\circ}C$, 100mtorr의 진공분위기에서 열처리한 YMnO$_3$박막은 $Y_2$O$_3$가 삽입된 경우 memory window 값이 $Y_2$O$_3$가 삽입되지 않은 경우보다 더 큰 값을 보였으며 5V에서 1.3V의 값을 보였다.

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p-Si 기판에 성장한 BaTiO3 박막의 두께와 구조적 특성과의 관계 (Relationship between Thin Film Thickness and Structural Properties of BaTiO3 Thin Films Grown on p-Si Substrates)

  • 민기득;이종원;김선진
    • 한국재료학회지
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    • 제23권6호
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    • pp.334-338
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    • 2013
  • In this study, $BaTiO_3$ thin films were grown by RF-magnetron sputtering, and the effects of the thin film thickness on the structural characteristics of $BaTiO_3$ thin films were systematically investigated. Instead of the oxide substrates generally used for the growth of $BaTiO_3$ thin films, p-Si substrates which are widely used in the current semiconductor processing, were used in this study in order to pursue high efficiency in device integration processing. For the crystallization of the grown thin films, annealing was carried out in air, and the annealing temperature was varied from $700^{\circ}C$. The changed thickness was within 200 nm~1200 nm. The XRD results showed that the best crystal quality was obtained for ample thicknesses 700 nm~1200 nm. The SEM analysis revealed that Si/$BaTiO_3$ are good quality interface characteristics within 300 nm when observed thickness. And surface roughness observed of $BaTiO_3$ thin films from AFM measurement are good quality surface characteristics within 300 nm. Depth-profiling analysis through GDS (glow discharge spectrometer) showed that the stoichiometric composition could be maintained. The results obtained in this study clearly revealed $BaTiO_3$ thin films grown on a p-Si substrate such as thin film thickness. The optimum thickness was 300 nm, the thin film was found to have the characteristics of thin film with good electrical properties.

Electrical and Optical Properties of p-type ZnO:P Fabricated by Ampoule-tube Vapor-state Diffusion

  • So, Soon-Jin;Oh, Sang-Hyun;Park, Choon-Bae
    • Transactions on Electrical and Electronic Materials
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    • 제9권1호
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    • pp.24-27
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    • 2008
  • ZnO has intensively attracted interest for the next generation of short wavelength LEDs and semiconductor lasers. However, for the development and application of the devices based on this material, the fabrication of p-type ZnO thin films is pivotal. Generally, the process of preparation of ZnO is unavoidably accompanied by the natural donor ions such as interstitial Zn ions and oxygen vacancy ions that show n-type electrical property and make fabrication of p-type ZnO to be a hard problem. On this study, to realize stable high-quality p-type ZnO thin films, the undoped ZnO thin films were diffused with P in vapor state. The ZnO:P thin films showed high-quality p-type properties electrically and optically.

STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구 (A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure)

  • 엄금용;오환술
    • 한국전기전자재료학회논문지
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    • 제13권9호
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    • pp.729-734
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    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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CVD법을 이용한 그래핀합성에 미치는 온도와 압력의 영향 (Influence of Temperature and Pressure on Graphene Synthesis by Chemical Vapor Deposition)

  • 이은영;김성진;전흥우
    • 열처리공학회지
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    • 제28권1호
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    • pp.7-16
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    • 2015
  • The fabrication of high quality graphene using chemical vapor deposition (CVD) method for application in semiconductor, display and transparent electrodes is investigated. Temperature and pressure have major impact on the growth of graphene. Graphene doping was obtained by deposition of $MoO_3$ thin films using thermal evaporator. Bilayer graphene and the metal layer graphene were obtained. According to the behavior of graphene growth P-type doping was confirmed. Graphene obtained through experiments was analyzed using optical microscopy, Raman spectroscopy, UV-visible light spectrophotometer, 4-point probe sheet resistance meter and atomic force microscopy.

미세홈 가공시 전해 인프로세스 드레싱의 영향에 관한 연구 (A Study on the Effect of Electrolytic In-process Dressing in Slot Grinding)

  • 유정봉;이석우;정해도;최헌종
    • 한국정밀공학회지
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    • 제16권1호통권94호
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    • pp.18-25
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    • 1999
  • Chipping is an unavoidable phenomenon in the slot grinding process of hard and brittle materials. However, it should be reduced for the improvement of surface integrity in the manufacture of optical and semiconductor components. Electrolytic In-process Dressing (ELID) technique for metal bonded superabrasive grinding wheel has been developed for mirror surface grinding of hard and brittle materials. Electrically dressed wheel surface has sharply exposed abrasives and results in lower grinding force, higher grinding efficiency in grinding. The paper deals with a newly developed method for slot grinding using ELID and was implemented to improve grooved surface quality and decreases chipping size on the edge of the groove. As a result, we accomplished chipping-free grooves and obtained the clear ground surfaces on glass and WC.

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Slot Grinding시 전해 인프로세스 드레싱의 영향에 관한 연구 (Effect of Electrolytic In-process Dressing in Slot Grinding)

  • 유정봉;정해도;최헌종
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1995년도 추계학술대회 논문집
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    • pp.48-52
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    • 1995
  • Chipping is an unavidable phenomean in the slot grinding process of hard and brittle materials. However,it should be reduced for the improvement of surface integrity in the manufacture of optical and semiconductor components. Electrolytic In-process Dressing (ELID) technique for metal bonded superabrasive grinding wheel has been developed for mirror surface grinding of hard and brittle materials. Electrically dressed wheel surface has sharply exposed abrasives and results in lower grinding force, higher grinding efficiency in grinding. The paper deals with a newly developed method for slot grinding using ELID and was implemented to improve grooved surface quality and decreases chipping size on the edge of the groove. As a result, we accomplished shipping-free grooves and obtained the clear ground sufaces on glass and tungsten carbide.

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액상에서의 엑시머 레이저 실리콘 미세가공 (Excimer laser micromachining of silicon in liquid phase)

  • 장덕석;김동식
    • 한국레이저가공학회지
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    • 제11권1호
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    • pp.12-18
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    • 2008
  • Laser micromachining is a promising technique to fabricate the micro-scale devices. However, there remains important challenges to reducethe redeposition of ablated materials around the laser irradiated zone and to get a smooth surface, especially for metal and semiconductor materials. To achieve the high-quality micromachined devices, various methods have been developed. Liquid-assisted micromachining can be a good solution to overcome the previously mentioned problems. During the laser ablation process, the liquid around the solid sample dramatically changes the ablation characteristics, such as ablation rate, surface profile, formation of debris, and so on. In this investigation, we conducted the laser micromachining of Si in various liquid environmental conditions, such as liquid types, liquid thickness. In addition, using nanoscale time-resolved shadowgraphy technique, we observed the ablation process in liquid environments to understand the mechanism of liquid-assisted laser micromachining.

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SWIR 이미지 센서 기술개발 동향 및 응용현황

  • 이재웅
    • 세라미스트
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    • 제21권2호
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    • pp.59-74
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    • 2018
  • Imaging in the Short Wave Infrared (SWIR) provides several advantages over the visible and near-infrared regions: enhanced image resolution in in foggy or dusty environments, deep tissue penetration, surveillance capabilities with eye-safe lasers, assessment of food quality and safety. Commercially available SWIR imagers are fabricated by integrating expensive epitaxial grown III-V compound semiconductor sensors with Si-based readout integrated circuits(ROIC) by indium bump bonding Infrared image sensors made of solution-processed quantum dots have recently emerged as candidates for next-generation SWIR imagers. They combine ease of processing, tunable optoelectronic properties, facile integration with Si-based ROIC and good performance. Here, we review recent research and development trends of various application fields of SWIR image sensors and nano-materials capable of absorption and emission of SWIR band. With SWIR sensible nano-materials, new type of SWIR image sensor can replace current high price SWIR imagers.