• IE interfaces
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• v.17 no.spc
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• pp.131-140
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• 2004

The purpose of this paper is to develop and show the efficiency of the URL(Unload Request Logic) and LRL(Load Request Logic) of the dispatcher in the Fab(Fabrication) Manufacturing Execution System. These logics are the core procedures which control the material(wafer and glass substrate) flow efficiently in the semiconductor and LCD fab considering inter-bay as well as intra-bay material flow. We use the present and future status information of the system by look-ahead and the information about the future transportation schedule of Automated Guided Vehicles. The simulation results show that the URL and LRL presented in this paper reduce the average lead time, average and maximum WIP level, and the average available AGV waiting time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.125-126
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• 2005

Recently semiconductor devices are required more smaller scale and more powerful performance. For smaller scale of device, multilayer structure is proposed. And, for the higher performance, interconnection material is change to copper, because copper has high EM(Electro-migration)and low resistivity. Then copper CMP process is a great role in a multilayer formation of semiconductor. Copper process is different from aluminum process. ECP process is one of the copper processes. In this paper, we focused on the defects tendency by copper thickness which filled using ECP process. we observed hump high and dishing. Conclusively, hump hight reduced at copper thickness increased Also dishing reduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.5
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• pp.350-354
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• 2020

In this study, a pressure sensor for each displacement was fabricated based on the silicon-based pressure sensor obtained through simulation results. Wires were bonded to the pressure sensor, and a piezoresistive pressure sensor was inserted into the printed circuit board (PCB) base by directly connecting a micro-electro-mechanical system (MEMS) sensor and a readout integrated circuit (ROIC) for signal processing. In addition, to prevent exposure, a non-conductive liquid silicone was injected into the sensor and the entire ROIC using a pipette. The packaging proceeded to block from the outside. Performing such packaging, comparing simple contact with strong contact, and confirming that the measured pulse wavelength appears accurately.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.187-192
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• 2012

Development of new efficient, high voltage switching devices with wide safe operating area and low on-state losses has received considerable attention in recent years. One of those structures with a very effective geometrical design is the trench gate Insulated Gate Bipolar Transistor(IGBT).power IGBT devices are optimized for high-voltage low-power design, decided to aim. Class 1,200 V NPT Planer IGBT, 1,200 V NPT Trench IGBT for class has been studied.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.283-285
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• 2001

In this paper, a new lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n+ cathode region. The improvement of latch-up performance is verified using the two-dimensional simulator MEDICI and the simulation results on the latch-up current density are 3.12${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the proposed LIGBT and 0.94${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.533-538
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• 2001

The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.8
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• pp.904-909
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• 2004

We studied the dielectric properties and voltage dependence on slice XLPE sheet from 22 kV and 154 kV power cables. Interface structures are XLPE/semiconductor and XLPE/water/semiconductor capacitance and tan6 of 22 kV, 154 kV were 52/42 pF and $7.4\times{10}/^{-4}, 2.15\times{10}^{-4}$, respectively in these results, the trend was increased with the increase of temperature the tan$\delta$ of XLPE/semiconductive layer and XLPE/water/ semiconductive layer were increased as compared with that of XLPE Temperature reliability of tan$\delta$ was small.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.34-37
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• 2004

Recently advancing mobile communication tools and I.T industry, semiconductor device is requested more integrated, faster operation time and more scaled-down. Because of these reasons semiconductor device is requested multilayer interconnection. For the multilayer interconnection chemical mechanical polishing (CMP) becomes one of the most useful process in semiconductor manufacturing process. In this experiment, we focus on understand the characterize and improve the CMP technology by control of slurry flow rate. Consequently, we obtain that optimal flow rate of slurry is 170ml/min, since optimal conditions are less chemical flow and performance high with good selectivity to Ta. If we apply this results to copper CMP process. it is thought that we will be able to obtain better yield.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.357-360
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• 2003

In this paper, we designed 4.5kV/1.5kA IGCT devices. GCT thyristor has many superior characteristics compared with GTO thyristor, for examples; snubberless turn-off capability, short storage time, high turn-on capability, small turn-off gate charge and low total power loss of the application system containing device and peripheral parts such as anode reactor and snubber capacitance. In this paper we designed GCT thyristor devices, and analyzed static and dynamic characteristics of GCT thyristor depending on the minority carrier lifetime, n-base thickness and doping concentration of n-base region, respectively. Especially, turn-on and turn-off characteristics are very important characteristics for GCT thyristor devices. So, we considered above characteristic for design and analysis of GCT devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.126-127
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• 2005

Semiconductor carbon nanotube was grown on oxided silicon wafer with Atmosphere Pressure Chemical Vapor Deposition (APCVD) ethmod and investigated the electrical property after thermal oxidation at 300$^{\circ}C$ in air. The electrical property was measured at room temperature in air after thermal oxidation at 300$^{\circ}C$ for various times in air. Semiconductor carbon nanotube was steadily changed to metallic carbon nanotube as increasing of thermal oxidation times at 300$^{\circ}C$ in air.