• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.545-545
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• 2008

Poly-Si is an essential material for floating gate in NAND Flash memory. To fabricate this material within region of floating gate, chemical mechanical polishing (CMP) is commonly used process for manufacturing NAND flash memory. We use colloidal silica abrasive with alkaline agent, polymeric additive and organic surfactant to obtain high Poly-Si to SiO2 film selectivity and reduce surface defect in Poly-Si CMP. We already studied about the effects of alkaline agent and polymeric additive. But the effect of organic surfactant in Poly-Si CMP is not clearly defined. So we will examine the function of organic surfactant in Poly-Si CMP with concentration separation test. We expect that surface roughness will be improved with the addition of organic surfactant as the case of wafering CMP. Poly-Si wafer are deposited by low pressure chemical vapor deposition (LPCVD) and oxide film are prepared by the method of plasma-enhanced tetra ethyl ortho silicate (PETEOS). The polishing test will be performed by a Strasbaugh 6EC polisher with an IC1000/Suba IV stacked pad and the pad will be conditioned by ex situ diamond disk. And the thickness difference of wafer between before and after polishing test will be measured by Ellipsometer and Nanospec. The roughness of Poly-Si film will be analyzed by atomic force microscope.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.190-191
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• 2006

We have investigated optical properties of Si/graded-$Si_{1-x}Ge_x$/Si heterostructures grown by reduced pressure chemical vapor deposition. Compared to standard condition using Si(100) substrate and growth temperature of $650^{\circ}C$, Si(111) resulted in low growth rate and high Ge mole fraction. Also samples grown at higher temperatures exhibited increased growth rate and reduced Ge mole fraction. The features regarding both substrate temperature and crystal orientation, representing high incorporation of silicon supplied from gas stream played as a key parameter, illustrate that reaction control were prevailed in this process growth condition. Using secondary ion mass spectroscopy and spectroscopic ellipsometry, microscopic changes in atomic components could be analyzed for Si/graded-$Si_{1-x}Ge_x$/Si heterostructures.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.77-81
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• 2019

Recently, Korea has been making efforts at the government level to overcome the national crisis that Japan's dependency on technology in the semiconductor and display materials sectors has also escaped due to export regulations on three materials carried out by Japan. Therefore, based on the data of the National Science & Technology Information Service (NTIS) operated by the government, we analyze the trend of R & D investment in the display field, thereby improving R & D to improve material technology competitiveness in the future. Let's examine the implications of investment. A total of 5 years of new research and development investment in the field of display was invested as basic research fund for 25%, 15% for applied research, and 53% for development research. In terms of development cost and development period, the basic research showed that the amount of money and the development period were shorter than that of applied research. In other words, the basic research accounted for 25% of the R & D investment and the average R & D period was only 3.2 years. As we can see from the recent development of H fiber carbon fiber, which was recently developed and entered full-scale production, we were able to succeed because of the benefits of government support for 10 years while giving the same material title differently. In order to escape from Japan's technological dependence on semiconductor and display materials in Korea, As such, basic research in the field of materials is only possible when long-term research is conducted.

• Proceedings of the Korean Magnestics Society Conference
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• 2008.12a
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• pp.302.2-302.2
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• 2008

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2004.11a
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• pp.330-330
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• 2004

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.364-364
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• 2010

In the electricity control field, a relay is the most widely used electrical switch. But it has problems about a material transfer phenomenon, contact bounce, and the mechanical life. These Problems cause the serious problem in a facility. So, we tried to solve these problems by applying MOSFET electronic switch and could find good improvement compared to conventional electrical switch.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.91-93
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• 2002

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.9
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• pp.667-670
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• 2010

In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.666-670
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• 2004

VLSI 소자에서 design rule(D/R)이 작아져 각 단위 Pattern의 size가 작아짐에 따라 aspect ratio가 커지게 되었다. 산화막 contact etch를 하는데 있어 산화막 측벽을 보호하는데, 이러한 보호막은 주로 fluoro-carbon 계열의 polymer precursor들이 사용된다. Aspect ratio(A/R)가 5 이하일 때에는 측벽의 보호막에 의한 바닥 변형이 문제가 되지 않으나, 10 이상의 A/R를 가진 contact에서는 크기가 줄고, 모양이 불균형하게 변하는 바닥 변형을 쉴게 관찰할 수 있다. 이러한 바닥 변형이 커지면 contact 저항이 높아지는 것은 물론이고, 심하게는 하부 pattern과 overlap 불량을 유발할 수 있다. 본 논문에서는 바닥변형을 일으키는 원인을 분석하고 fluoro-carbon 계열의 polymer precursor의 종류$(C_4_F6\;vs.\;C_3F_8)$에 따른 polymer증착 상태 확인 및 pattern비대칭에 따른 바닥 변형의 고찰과 plasma etching 시 H/W 변형을 통해 바닥 변형이 거의 없는 조건을 찾아낼 수 있었다.