• Title/Summary/Keyword: semiconductor manufacturing process

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Fault Detection of Unbalanced Cycle Signal Data Using SOM-based Feature Signal Extraction Method (SOM기반 특징 신호 추출 기법을 이용한 불균형 주기 신호의 이상 탐지)

  • Kim, Song-Ee;Kang, Ji-Hoon;Park, Jong-Hyuck;Kim, Sung-Shick;Baek, Jun-Geol
    • Journal of the Korea Society for Simulation
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    • v.21 no.2
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    • pp.79-90
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    • 2012
  • In this paper, a feature signal extraction method is proposed in order to enhance the low performance of fault detection caused by unbalanced data which denotes the situations when severe disparity exists between the numbers of class instances. Most of the cyclic signals gathered during the process are recognized as normal, while only a few signals are regarded as fault; the majorities of cyclic signals data are unbalanced data. SOM(Self-Organizing Map)-based feature signal extraction method is considered to fix the adverse effects caused by unbalanced data. The weight neurons, mapped to the every node of SOM grid, are extracted as the feature signals of both class data which are used as a reference data set for fault detection. kNN(k-Nearest Neighbor) and SVM(Support Vector Machine) are considered to make fault detection models with comparisons to Hotelling's $T^2$ Control Chart, the most widely used method for fault detection. Experiments are conducted by using simulated process signals which resembles the frequent cyclic signals in semiconductor manufacturing.

A New Manufacturing Technology and Characteristics of Trench Gate MOSFET (새로운 트렌치 게이트 MOSFET 제조 공정기술 및 특성)

  • Baek, Jong-Mu;Cho, Moon-Taek;Na, Seung-Kwon
    • Journal of Advanced Navigation Technology
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    • v.18 no.4
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    • pp.364-370
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    • 2014
  • In this paper, high reliable trench formation technique and a novel fabrication techniques for trench gate MOSFET is proposed which is a key to expend application of power MOSFET in the future. Trench structure has been employed device to improve Ron characteristics by shrinkage cell pitch size in DMOSFET and to isolate power device part from another CMOS device part in some power integrated circuit. A new process method for fabricating very high density trench MOSFETs using mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width and source and p=body region with a resulting increase in cell density and current driving capability and decrease in on resistance.

Implementation of Speed Limitation Controller Considering Motor Parameter Variation in High Speed Operation (모터 파라미터 산포를 고려한 고속 운전에서의 속도제한 제어기 구현)

  • Kim, Kyung-Hoon;Yun, Chul;Kwon, Woo-Hyen
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.11
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    • pp.1584-1590
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    • 2017
  • This paper presents a implementation method of reliable speed limitation controller considering motor parameter variation in high speed operation. In spinning process of drum washing machine, speed increase has to be limited when unallowable imbalance mass is detected. Otherwise, severe noise and vibration can happen because noise and vibration are proportional to imbalance mass. To detect imbalance mass, d-axis current magnitude is used. However, we have to compensate for back-emf and power supply variation by means of detecting them because d-axis current is affected by both of them. On the other hand, we have to carefully estimate back-emf because back-emf is affected by stator resistance variation and inverter voltage error. Stator resistance variation can happen by manufacturing process for mass production or temperature variation in running. And there are inverter voltage errors between command voltage from micro-computer to inverter and real voltage from inverter to motor because of rising and falling time delay and turn-on resistance of power semiconductor switch. To solve this problem, we propose 2-step align current injection method which is to inject step-wise current right before starting. By this method, we can simply obtain stator resistance by ratio of voltage without inverter voltage error and current, and we can measure inverter voltage error. So we can obtain more exact model current, and then by simple calculation with compensation gain, we can estimate more accurate motor back-emf. We show that this method works well. It is verified through experiments.

A Study on The Improvement of Profile Tilting or Bottom Distortion in HARC (높은 A/R의 콘택 산화막 에칭에서 바닥모양 변형 개선에 관한 연구)

  • Hwang, Won-Tae;Kim, Gli-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.5
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    • pp.389-395
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    • 2005
  • The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.

Characteristics of Sapphire Wafers Polishing Depending on Ion Conductivity of Silica Sol (실리카졸의 이온전도도 변화에 따른 사파이어 웨이퍼의 연마 특성)

  • Na, Ho Seong;Cho, Gyeong Sook;Lee, Dong-Hyun;Park, Min-Gyeong;Kim, Dae Sung;Lee, Seung-Ho
    • Korean Journal of Materials Research
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    • v.25 no.1
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    • pp.21-26
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    • 2015
  • CMP(Chemical Mechanical Polishing) Processes have been used to improve the planarization of the wafers in the semiconductor manufacturing industry. Polishing performance of CMP Process is determined by the chemical reaction of the liquid sol containing abrasive, pressure of the head portion and rotational speed of the polishing pad. However, frictional heat generated during the CMP process causes agglomeration of the particles and the liquidity degradation, resulting in a non-uniform of surface roughness and surface scratch. To overcome this chronic problem, herein, we introduced NaCl salt as an additive into silica sol for elimination the generation of frictional heat. The added NaCl reduced the zata potential of silica sol and increased the contact surface of silica particles onto the sapphire wafer, resulting in increase of the removal rate up to 17 %. Additionally, it seems that the silica particles adsorbed on the polishing pad decreased the contact area between the sapphire water and polishing pad, which suppressed the generation of frictional heat.

A Study on the Circuit Design Method of CNTFET SRAM Considering Carbon Nanotube Density (탄소나노튜브 밀도를 고려한 CNTFET SRAM 디자인 방법에 관한 연구)

  • Cho, Geunho
    • Journal of IKEEE
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    • v.25 no.3
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    • pp.473-478
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    • 2021
  • Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.

A Method to Adjust Cyclic Signal Length Using Time Invariant Feature Point Extraction and Matching(TIFEM) (시불변 특징점 추출 및 정합을 이용한 주기 신호의 길이 보정 기법)

  • Han, A-Hyang;Park, Cheong-Sool;Kim, Sung-Shick;Baek, Jun-Geol
    • Journal of the Korea Society for Simulation
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    • v.19 no.4
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    • pp.111-122
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    • 2010
  • In this study, a length adjustment algorithm for cyclic signals in manufacturing process using Time Invariant Feature point Extraction and Matching(TIFEM) is proposed. In order to precisely compensate the length of cyclic signals which have irregular length in the middle of signal as well as in the full length more feature points are needed. The extracted feature must involve information about the pattern of signal and should have invariant properties on time and scale. The proposed TIFEM algorithm extracts features having the intrinsic properties of the signal characteristics at first. By using those extracted features, feature vector is constructed for each time point. Among those extracted features, the only effective features are filtered and are chosen such as basis for the length adjustment. And then the partial length adjustment is performed by matching feature points. To verify the performance of the proposed algorithm, the experiments were performed with the experimental data mimicking the three kinds of signals generated from the actual semiconductor process.

A Study on the Estimation of the GHGs Emissions to the Reuse of De-ionized Water Production Process in Semiconductor Factory (반도체 생산용 초순수 제조공정의 농축수 재이용에 따른 온실가스 발생량 평가에 관한 연구)

  • Han, Jong-Min;Chung, Jin-Do;Kim, San
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.9
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    • pp.518-525
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    • 2018
  • In the 21st century, human beings are becoming increasingly concerned about greenhouse gas emissions as the environment changes due to climate change become serious. The temperature of Korea has risen by approximately $1.5^{\circ}C$ from 1904 to 2000, and the climate is changing gradually to a subtropical climate. As a result, the frequency of floods and droughts increases, so that the water available to humans is decreasing every year, and the cost of using city water is rising every year. The reuse of wastewater that is normally abandoned is inevitable. This study examined the monthly data for 6 months of operation by installing a reuse system of concentrated wastewater (Re R/O System) that is generated during the process of manufacturing de-ionized water (DI-Water System) used in semiconductor processing. As a result of the survey, the city water supply saved approximately $2,767m^3$ per month. The average annual greenhouse gas emissions was $1,329.07kg-CO_2$ per month due to the electricity consumption of the water reuse system. On the other hand, because of the reduction in city water supply, the average monthly average of $918.64kg-CO_2$ was reduced, and the greenhouse gas emissions were increased to $410.43kg-CO_2$ per month. If it improves some processes in the water reuse system, the amount of greenhouse gas emissions can be reduced by an average of $254.41kg-CO_2$ per month.

Wafer bin map failure pattern recognition using hierarchical clustering (계층적 군집분석을 이용한 반도체 웨이퍼의 불량 및 불량 패턴 탐지)

  • Jeong, Joowon;Jung, Yoonsuh
    • The Korean Journal of Applied Statistics
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    • v.35 no.3
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    • pp.407-419
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    • 2022
  • The semiconductor fabrication process is complex and time-consuming. There are sometimes errors in the process, which results in defective die on the wafer bin map (WBM). We can detect the faulty WBM by finding some patterns caused by dies. When one manually seeks the failure on WBM, it takes a long time due to the enormous number of WBMs. We suggest a two-step approach to discover the probable pattern on the WBMs in this paper. The first step is to separate the normal WBMs from the defective WBMs. We adapt a hierarchical clustering for de-noising, which nicely performs this work by wisely tuning the number of minimum points and the cutting height. Once declared as a faulty WBM, then it moves to the next step. In the second step, we classify the patterns among the defective WBMs. For this purpose, we extract features from the WBM. Then machine learning algorithm classifies the pattern. We use a real WBM data set (WM-811K) released by Taiwan semiconductor manufacturing company.

A New Cleaning Concept for Display Manufacturing Process with Electrolyzed Anode Water (전해 양극수를 이용한 새로운 디스플레이 세정)

  • Ryoo Kunkul
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.6 no.1
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    • pp.78-82
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    • 2005
  • Display manufacturing process has adopted RCA cleaning, applying to larger area and coping with environmental issue for last ten years. However, the approaching concept of ozonized, hydrogenised, or electrolyzed water cleaning technologies is within RCA clean paradigm. In this work, only electrolyzed anode water was applied to clean particles and organics as well as metals based on Pourbaix concept, and as a test vehicle, MgO particles were introduced to prove the new concept. The electrolyzed anode water is very oxidative with high oxidation reduction potential (ORP) and low in pH of more than 900 mV and 3.1, respectively. MgO particles were immersed in the anode water and its weight losses due to dissolution were measured with time. Weight losses were in the ranges of 100 to 500 micrograms in 250 ml anode water depending on their ORP and pH. Therefore it was concluded that the cleaning radicals in the anode water was at least in the range of 1 to $5{\times}10^{20}$ ea per 250 ml anode water equivalent to $1{\times}10^{18} ea/cm^2$. Hence it can be assumed that the anode water applied to display cleaning from now on $1{\times}10^{10}$ to $1{\times}10^{15} ea/cm^2$ ranges of contaminants are being treated. In addition, it was observed that anode water did not develop micro-roughness on hydrophobic surface while it did on the native silicon oxide.

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