• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.6
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• pp.572-578
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• 2015

Yield prediction is one of the most important issues in semiconductor manufacturing. Especially, for a fast-changing environment of the semiconductor industry, accurate and reliable prediction techniques are required. In this study, we propose a prediction model to predict wafer yield based on virtual metrology process parameters in semiconductor manufacturing. The proposed prediction model addresses imbalance problems frequently encountered in semiconductor processes so as to construct reliable prediction model. The effectiveness and applicability of the proposed procedure was demonstrated through a real data from a leading semiconductor industry in South Korea.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.10
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• pp.103-112
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• 1998

The evolution of semiconductor manufacturing technology has accelerated the reduction of device dimensions and the increase of integrated circuit density. In order to improve yield within a short turn around time and maintain it at high level, a system that can rapidly determine problematic processing steps is needed. The statistical process control detects abnormal process variation of key parameters. Expert systems in SPC can serve as a valuable tool to automate the analysis and interpretation of control charts. A set of IF-THEN rules was used to formalize knowledge base of special causes. This research proposes a strategy to apply expert system to SPC in semiconductor manufacturing. In analysis, the expert system accomplishes the instability detection of process parameter, In diagnosis, an engineer is supported by process analyzer program. An example has been used to demonstrate the expert system and the process analyzer.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.4
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• pp.415-424
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• 2002

Semiconductor manufacturing has been emerged as a highly competitive but profitable business. Accordingly it becomes very important for semiconductor manufacturing companies to meet customer demands at the right time, in order to keep the leading edge in the world market. However, due-date oriented production is very difficult task because of the complex job flows with highly resource conflicts in fabrication shop called FAB. Due to its cyclic manufacturing feature of products, to be completed, a semiconductor product is processed repeatedly as many times as the number of the product manufacturing cycles in FAB, and FAB processes of individual manufacturing cycles are composed with similar but not identical unit processes. In this paper, we propose a production scheduling and control scheme that is designed specifically for semiconductor scheduling environment (FAB). The proposed scheme consists of three modules: simulation module, cycle due-date estimation module, and dispatching module. The fundamental idea of the scheduler is to introduce the due-date for each cycle of job, with which the complex job flows in FAB can be controlled through a simple scheduling rule such as the minimum slack rule, such that the customer due-dates are maximally satisfied. Through detailed simulation, the performance of a cycle due-date based scheduler has been verified.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.9
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• pp.1330-1335
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• 2012

This paper proposes an automatic measurement sampling method for the semiconductor manufacturing process. The method recommends sampling rates using information of process capability indexes and production scheduling plan within the restricted metrology capacity. In addition, it automatically controls the measurement WIP (Work In Process) using measurement priority values to minimize the measurement risks and optimize the measurement capacity. The proposed sampling method minimizes measurement controls in the semiconductor manufacturing process and improves the fabrication productivity via reducing measurement TAT (Turn Around Time), while guaranteeing the level of process quality.

• Analytical Science and Technology
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• v.5 no.4
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• pp.455-464
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• 1992

Using FT-IR, we determined the depth of silylated layers produced from various gas-phase-silylation conditions was proposed by using Fourier Transform Infrared (FT-IR) spectroscopic analysis. The depth of silylated layer was determined from absorbance measurments of the significant peaks (Si-O-ph, Si-C, Si-H) of FT-IR spectra with background spectrum subtraction method. And the results were compared with thickness measurments of SEM. The results were well agree with SEM. It found to be well suited for determining silylation process window.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.124-128
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• 2023

Semiconductor engineers have long sought to enhance the energy efficiency of mobile semiconductors by reducing their voltage. During the final stages of the semiconductor manufacturing process, the screening and evaluation of voltage is crucial. However, determining the optimal test start voltage presents a significant challenge as it can increase testing time. In the semiconductor manufacturing process, a wealth of test element group information is collected. If this information can be controlled to predict the test voltage, it could lead to a reduction in testing time and increase the probability of identifying the optimal voltage. To achieve this, this paper is exploring machine learning techniques, such as linear regression and ensemble models, that can leverage large amounts of information for voltage prediction. The outcomes of these machine learning methods not only demonstrate high consistency but can also be used for feature engineering to enhance accuracy in future processes.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.101-105
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• 2011

In case of high-tech process industries such as semiconductor and TFT-LCD manufactures, fault of a virtually finished product that is value-added one, since it has gone throughout the most of processes, may give rise to quality cost nearly amount to its selling price and can be a main cause that decreases the efficiency of manufacturing process. This paper proposes a real-time dispatching algorithm for semiconductor manufacturing process with rework. In order to evaluate the proposed algorithm, this paper examines the performance of the proposed method by comparing it with that of the existing dispatching algorithms, based on various experimental data.

• Journal of Korean Institute of Industrial Engineers
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• v.38 no.1
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• pp.46-56
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• 2012

The purpose of virtual metrology (VM) in semiconductor manufacturing is to predict every wafer's metrological values based on its process equipment data without an actual metrology. In this paper, we propose novelty detection-based reliability estimation models for VM in order to support flexible utilization of VM results. Because the proposed model can not only estimate the reliability of VM, but also identify suspicious process variables lowering the reliability, quality control actions can be taken selectively based on the reliance level and its causes. Based on the preliminary experimental results with actual semiconductor manufacturing process data, our models can successfully give a high reliance level to the wafers with small prediction errors and a low reliance level to the wafers with large prediction errors. In addition, our proposed model can give more detailed information by identifying the critical process variables and their relative impacts on the low reliability.

• IE interfaces
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• v.13 no.3
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• pp.348-357
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• 2000

SCM(Supply Chain Management) is a new approach to satisfy customers via an integrated management for the whole business processes of the manufacturing from the raw material procurement to the product or service delivery to customers. Typically the semiconductor industry is the one whose supply chain network is distributed all over the world, and its manufacturing process has the particular characteristics which has to be considered in the modeling of supply chain. In this paper we suggest the push and pull type supply chain models based on the manufacturing characteristics and their mathematical formulation for the semiconductor industry. Push supply chain model pursuits the high throughput and the balance of the WIP flow, and pull supply chain model does to minimize the total cost of order-based manufacturing, distribution and transportation process in order to meet customer's request appropriately.