• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.6
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• pp.37-43
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• 2017

This review investigates the basic principle of physical interactions and failure mechanisms introduced in the materials and inner parts of semiconducting components under electromagnetic pulses (EMPs). The transfer process of EMPs at the semiconducting component level can be explained based on three layer structures (air, dielectric, and conductor layers). The theoretically absorbed energy can be predicted by the complex reflection coefficient. The main failure mechanisms of semiconductor components are also described based on the Joule heating energy generated by the coupling between materials and the applied EMPs. Breakdown of the P-N junction, burnout of the circuit pattern in the semiconductor chip, and damage to connecting wires between the lead frame and semiconducting chips can result from dielectric heating and eddy current loss due to electric and magnetic fields. To summarize, the EMPs transferred to the semiconductor components interact with the chip material in a semiconductor, and dipolar polarization and ionic conduction happen at the same time. Destruction of the P-N junction can result from excessive reverse voltage. Further EMP research at the semiconducting component level is needed to improve the reliability and susceptibility of electric and electronic systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.371-375
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• 2019

Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a $SiO_2/Si_3N_4$ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.6-10
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• 2020

The silver nanowires (AgNWs) were synthesized by the conventional polyol process, which revealed 25 ㎛ and 30 nm of average length and diameter, respectively. The synthesized AgNWs were applied to the CdSe/CdZnS quantum dot (QD) based transparent light-emitting device (LED). The device using a randomly networked AgNWs electrode had some problems such as the high threshold voltage (for operating the device) due to the random pores from the networked AgNWs. As a method of improvement, a composite electrode was formed by overlaying the ZnO:Ga on the AgNWs network. The device used the composite electrode revealed a low threshold voltage (4.4 Vth) and high current density compared to the AgNWs only electrode device. The brightness and current density of the device using composite electrode were 55.57 cd/㎡ and 41.54 mA/㎠ at the operating voltage of 12.8 V, respectively, while the brightness and current density of the device using (single) AgNWs only were 1.71 cd/㎡ and 2.05 mA/㎠ at the same operating voltage. The transmittance of the device revealed 65 % in a range of visible light. Besides the reliability of the devices was confirmed that the device using the composite electrode revealed 2 times longer lifetime than that of the AgNWs only electrode device.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.11-14
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• 2022

In this work, we evaluated the Al₂O₃ film, which was deposited by atomic layer deposition, degraded by exposure to harsh environments. The Al₂O₃ films deposited by atomic layer deposition have long been used as a gas diffusion barrier that satisfies barrier requirements for device reliability. To investigate the barrier and mechanical performance of the Al₂O₃ film with increasing temperature and relative humidity, the properties of the degraded Al₂O₃ film exposed to the harsh environment were evaluated using electrical calcium test and tensile test. As a result, the water vapor transmission rate of Al₂O₃ films stored in harsh environments has fallen to a level that is difficult to utilize as a barrier film. Through water vapor transmission rate measurements, it can be seen that the water vapor transmission rate changes can be significant, and the environment-induced degradation is fatal to the Al₂O₃ thin films. In addition, the surface roughness and porosity of the degraded Al₂O₃ are significantly increased as the environment becomes severer. the degradation of elongation is caused by the stress concentration at valleys of rough surface and pores generated by the harsh environment. Becaused the harsh envronment-induced degradation convert amorphous Al₂O₃ to crystalline structure, these encapsulation properties of the Al₂O₃ film was easily degraded.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.1-7
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• 2002

Modem technology depends on the reliability of extremely high precision equipments. In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a sub-micrometer. This equipment requires a vibration free environment to provide its proper function. Therefore, this high technology equipments require very strict environmental vibration criteria because it is used as basic data for the design of building structure and structural dynamics of equipment. In this paper, the new approach is proposed to investigate the mismatch problem of time and frequency domain for vibration criteria of sensitive equipment. The proposed approach is based on a vibration measurement data and a relative transfer function which can be obtained by experiment or analysis.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.263-266
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• 1990

In order to high-respone and high-reliability of devices, it depended upon how we can increase the high-frequency of the Inverter, UPS and it's application. but using high-frequency of self turn-off devices, it is important to reduce switching device loss and spike voltage of turn off. This paper proposed new methode about computer simulation of device loss also experimental results with switching device characteristic are presented.

• International Journal of Quality Innovation
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• v.8 no.1
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• pp.137-153
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• 2007

Failure mode and effects analysis (FMEA) is a preventive technique in reliability management field. The successful implementation of FMEA technique can avoid or reduce the probability of system failure and achieve good product quality. The FMEA technique had applied in vest scopes which include aerospace, automatic, electronic, mechanic and service industry. The marking process is one of the back ends testing process that is the final process in semiconductor process. The marking process failure can cause bad final product quality and return although is not a primary process. So, how to improve the quality of marking process is one of important production job for semiconductor testing factory. This research firstly implements FMEA technique in laser marking process improvement on semiconductor testing factory and finds out which subsystem has priority failure risk. Secondly, a CCD position solution for priority failure risk subsystem is provided and evaluated. According analysis result, FMEA and CCD position implementation solution for laser marking process improvement can increase yield rate and reduce production cost. Implementation method of this research can provide semiconductor testing factory for reference in laser marking process improvement.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.126-130
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• 2021

The ball grid array is one of the packaging methods that used in high density printed circuit board. Solder void defects caused by voids in the solder ball during the BGA process do not directly affect the reliability of the product, but it may accelerate the aging of the device on the PCB layer or interface surface depending on its size or location. Void inspection is important because it is related in yields with products. The most important process in the optical inspection of solder void is the segmentation process of solder and void. However, there are several segmentation algorithms for the vision inspection, it is impossible to inspect all of images ideally. When X-Ray images with poor contrast and high level of noise become difficult to perform image processing for vision inspection in terms of software programming. This paper suggests the solution to deal with the suggested problem by means of using Mask R-CNN instead of digital image processing algorithm. Mask R-CNN model can be trained with images pre-processed to increase contrast or alleviate noises. With this process, it provides more efficient system about complex object segmentation than conventional system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.1-8
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• 2006

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.370-377
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• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.