• Journal of Digital Contents Society
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• v.18 no.6
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• pp.1193-1198
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• 2017

The IGBT structure developed in this paper is used as a high power switch semiconductor for DC transmission and distribution and it is expected that it will be used as an important electronic device for new and long distance DC transmission in the future by securing fast switching speed and improved breakdown voltage characteristic. As a new type of next generation power semiconductors, it is designed to improve the switching speed while at the same time improving the breakdown voltage characteristics, reducing power loss characteristics, and achieving high current density advantages at the same time. These improved properties were obtained by further introducing SiO2 into the N-drift region of the Planar IGBT and were compared and analyzed using the Sentaurus TCAD simulation tool.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.260-263
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• 2003

When ICP(Inductive Coupled Plasma type etching and wafer manufacturing is being processed in semiconductor process, a noxious gas in PFC and CFC system is generated. Gas cleaning dry scrubber is to remove this noxious gas. This paper describes a power source device, 2MHz switching frequency class 2kW RF Generator, used as a main power source of the gas cleaning dry scrubber. The power stage of DC/DC converter is consist of full bridge type converter with 100kHz switching frequency Power amplifier is push pull type inverter with 2MHz switching frequency, and transmission line transformer. The adequacy of the circuit type and the reliability of generating plasma in various load conditions are verified through 50$\Omega$ dummy load and chamber experiments result.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• IE interfaces
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• v.17 no.1
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• pp.1-12
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• 2004

In a modern semiconductor device manufacturing industry, statistical bin limits on wafer level test bin data are used for minimizing value added to defective product as well as protecting end customers from potential quality and reliability excursion. Most wafer level test bin data show skewed distributions. By Monte Carlo simulation, this paper evaluates methods and sample size effect regarding determination of statistical bin limits. In the simulation, it is assumed that wafer level test bin data follow the Poisson distribution. Hence, typical shapes of the data distribution can be specified in terms of the distribution's parameter. This study examines three different methods; 1) percentile based methodology; 2) data transformation; and 3) Poisson model fitting. The mean square error is adopted as a performance measure for each simulation scenario. Then, a case study is presented. Results show that the percentile and transformation based methods give more stable statistical bin limits associated with the real dataset. However, with highly skewed distributions, the transformation based method should be used with caution in determining statistical bin limits. When the data are well fitted to a certain probability distribution, the model fitting approach can be used in the determination. As for the sample size effect, the mean square error seems to reduce exponentially according to the sample size.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1730-1733
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• 2007

As semiconductor and MEMS devices become smaller, testing process during their production should follow such a high density trend. A circuit inspection tool "probe card" makes contact with electrode pads of the device under test (DUT). Nowadays, electrode pads are irregularly arranged and have height difference. In order to absorb variations in the heights of electrode pads and to generate contact loads, contact probes must have some levels of mechanical spring properties. Contact probes must also yield a force to break the surface native oxide layer or contamination layer on the electrodes to make electric contact. In this research, new vertical micro contact probe with bellows shape is developed to overcome shortage of prior work. Especially, novel bellows shape is used to reduce stress concentration in this design and stopper is used to change the stiffness of micro contact probe. Variable stiffness can be one solution to overcome the height difference of electrode pads.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.108-114
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• 1999

Surface acoustic wave (SAW) device is very attractive for gas sensor applications because of their small size, low cost, high sensitivity, and good reliability. A dual delay line surface acoustic wave $NO_2$ gas sensors have been designed and fabricated on the $LiTaO_3$ piezoelectric single crystal substrate. The capacitance of the fabricated IDTs was 326.34pF at the frequency of 79.3MHz. The maximum reflection loss of the impedence-matched IDTs was -16.74dB at the frequency of 79.3MHz. The SAW oscillator was constructed and the stable oscillation was obtained by controlling the gain of rf amplifier properly. The oscillation frequency shift of the SAW oscillator to the $NO_2$ gas was 28Hz/ppm.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Journal of the Korean Society of Industry Convergence
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• v.25 no.3
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• pp.333-340
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• 2022

Recently, the use of large-capacity secondary batteries for electric vehicles is rapidly increasing, and accordingly, the demand for technologies and equipment for battery reliability evaluation is increasing significantly. The existing short circuit test equipment for evaluating the stability of the existing secondary battery consists of relays, MCs, and switches, so when a large current is energized during a short circuit, contact fusion failures occur frequently, resulting in high equipment maintenance and repair costs. There was a disadvantage that repeated testing was impossible. In this paper, we developed an electronic short circuit test device that realizes stable switching operation when a large-capacity power semiconductor switch is energized with a large current, and applied smart ICT technology to this electronic short circuit stability test system to achieve high speed and high precision through communication with the master. It is expected that the inspection history management system based on data measurement, database format and user interface will be utilized as essential inspection process equipment.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.409-414
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• 2017

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.