• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.9
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• pp.1060-1069
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• 2019

Pedestrian-based camera self-calibration methods are suitable for video surveillance systems since they do not require complex calibration devices or procedures. However, using arbitrary pedestrians as calibration targets may result in poor calibration accuracy due to the unknown height of each pedestrian. To solve this problem in the real surveillance environments, this paper proposes a novel Bayesian approach. By assuming known statistics on the height of pedestrians, we construct a probabilistic model that takes into account uncertainties in both the foot/head locations and the pedestrian heights, using foot-head homology. Since solving the model directly is infeasible, we use variational Bayesian inference, an approximate inference algorithm. Accordingly, this makes it possible to estimate the height of pedestrians and to obtain accurate camera parameters simultaneously. Experimental results show that the proposed algorithm is robust to noise and provides accurate confidence in the calibration.

• International Journal of Precision Engineering and Manufacturing
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• v.2 no.2
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• pp.11-16
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• 2001

This paper presents an in self-calibration method to corrent the Z-directional distortion of AFM(Atomic Force Microscopy).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.882-885
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• 2011

This paper presents testing and self-calibration of RF circuits using MEMS switches to identify process-related defects and out of specification circuits. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2435-2439
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• 2005

In case of visual sensing systems with multiple mirrors, systematic errors need to be reduced by the system calibration and the mirror position adjustment in order to enhance system measurement accuracy. In this paper, a self calibration method is presented for a visual sensing system designed to measure the three-dimensional information in deformable peg-in-hole tasks. It is composed of a CCD camera and a series of mirrors including two pyramidal mirrors. By using an image of the inner pyramidal mirror taken by the system, the error parameters of the inner pyramidal mirror could be calibrated or adjusted. Also the influence of the plane mirrors is investigated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.2
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• pp.536-544
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• 2017

Wireless RSSI (Received Signal Strength Indication) fingerprinting is one of the most popular methods for indoor positioning as it provides reasonable accuracy while being able to exploit existing wireless infrastructure. However, the process of radio map construction (aka fingerprint calibration) is laborious and time consuming as precise physical coordinates and wireless signals have to be measured at multiple locations of target environment. This paper proposes a method to build the map from a combination of RSSIs without location information collected in a crowdsourcing fashion, and a handful of labeled RSSIs using a semi-supervised self organizing map learning algorithm. Experiment on simulated data shows promising results as the method is able to recover the full map effectively with only 1% RSSI samples from the fingerprint database.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.10a
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• pp.137-137
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• 2003

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Korean Journal of Optics and Photonics
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• v.17 no.5
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• pp.391-395
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• 2006

In this paper, radiometric calibration of a FTIR spectrometer for passive remote sensing application was introduced and verified. Radiometric calibration is a significant signal processing procedure to retrieve the object radiance from the measured spectrum. The object radiance is measured and registered distorted by the detector's responsivity dependent on wavelength and instrument self-emission. Radiance of two temperature points, hot temperature and cold temperature, from a well-controlled blackbody was measured and used to obtain the scale factor and offset factor which are required for radiometric calibration. For gas phase C2H5OH. radiometric calibration was done and verified through comparison of its emission line width and intensity with the standard spectrum.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.59-64
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• 2006

The slope of the ramp generator in a single slope ADC(analog-to-digital converter) suffers from process and frequency variation. This variation in ramp slope causes ADC gain variation and eventually limits the performance of the ISP(image signal processing) in a CIS(CMOS image sensor) that uses the single slope ADC. This paper proposes a ramp slope BISC(built-in-self-calibration) scheme for CIS. The CIS with proposed BISC was fabricated with a $0.35{\mu}m$ process. The measurement results show that the proposed architecture effectively calibrate the ramp slope against process and clock frequency variation. The silicon area overhead is less than $0.7\%$ of the full chip area.